igc: move TXDCTL and RXDCTL related macros

Move and consolidate TXDCTL and RXDCTL macros in preparation for
upcoming TXDCTL changes. This improves organization and readability.

Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: Faizal Rahim <faizal.abdul.rahim@linux.intel.com>
Tested-by: Mor Bar-Gabay <morx.bar.gabay@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>

diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h
index 859a15e4ccbab577bb25ec158ac1aef4fbfa95c7..25695eada5633cd7871085f37cf2e6f92666ffda 100644 (file)
--- a/drivers/net/ethernet/intel/igc/igc.h
+++ b/drivers/net/ethernet/intel/igc/igc.h
@@ -487,10 +487,19 @@ static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc)
  */
 #define IGC_RX_PTHRESH                 8
 #define IGC_RX_HTHRESH                 8
+#define IGC_RX_WTHRESH                 4
+/* Ena specific Rx Queue */
+#define IGC_RXDCTL_QUEUE_ENABLE                0x02000000
+/* Receive Software Flush */
+#define IGC_RXDCTL_SWFLUSH             0x04000000
+
 #define IGC_TX_PTHRESH                 8
 #define IGC_TX_HTHRESH                 1
-#define IGC_RX_WTHRESH                 4
 #define IGC_TX_WTHRESH                 16
+/* Ena specific Tx Queue */
+#define IGC_TXDCTL_QUEUE_ENABLE                0x02000000
+/* Transmit Software Flush */
+#define IGC_TXDCTL_SWFLUSH             0x04000000
 
 #define IGC_RX_DMA_ATTR \
        (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)

diff --git a/drivers/net/ethernet/intel/igc/igc_base.h b/drivers/net/ethernet/intel/igc/igc_base.h
index 6320eabb72fe0d8334992e493b4c7dd1e81d5e64..eaf17cd031c3a55056591184fb56f71ad6f7e4a6 100644 (file)
--- a/drivers/net/ethernet/intel/igc/igc_base.h
+++ b/drivers/net/ethernet/intel/igc/igc_base.h
@@ -86,14 +86,6 @@ union igc_adv_rx_desc {
        } wb;  /* writeback */
 };
 
-/* Additional Transmit Descriptor Control definitions */
-#define IGC_TXDCTL_QUEUE_ENABLE        0x02000000 /* Ena specific Tx Queue */
-#define IGC_TXDCTL_SWFLUSH     0x04000000 /* Transmit Software Flush */
-
-/* Additional Receive Descriptor Control definitions */
-#define IGC_RXDCTL_QUEUE_ENABLE        0x02000000 /* Ena specific Rx Queue */
-#define IGC_RXDCTL_SWFLUSH             0x04000000 /* Receive Software Flush */
-
 /* SRRCTL bit definitions */
 #define IGC_SRRCTL_BSIZEPKT_MASK       GENMASK(6, 0)
 #define IGC_SRRCTL_BSIZEPKT(x)         FIELD_PREP(IGC_SRRCTL_BSIZEPKT_MASK, \