* Patch by Stefan Roese, 1 Mar 2002:

  - Added ORSG board
  - crc32 command extended - optionally write CRC to memory
  - CFG_DEVICE_NULLDEV for nulldev added

* Patch by Rich Ireland, 01 Mar 2002:
  add "disassemble" target

* Patch by Rich Ireland, 26 Feb 2002:
  enable RAM exceptions for the 74xx_7xx

* 2 patches by Stefan Roese, 26 Feb 2002:
  - esd boards: flash code updated (AMD 29LV320B/T added)
  - DU405 board: FPGA updated for new revision and RTC support added
  - 405gp_pci.c: Bug fixed in PCI configuration (Andrew May)
  - mc146818.c: support for memory mapped RTC added

  - 405gp_enet.c: rx and tx buffer descriptors now allocated (no
    fixed address used anymore), and some code cleanup
  - 405gp_pci.c: Removed PCI class code init for CPCI405 board

* Patch by Tom Angert, 25 Feb 2002:
  - Fix dependency of ELF loader on network support
  - allow offset into the first flash before a JFFS2 filesystem
  - fix idle bits in miiphybb.c

diff --git a/CHANGELOG b/CHANGELOG
index fa1038442e06bc95fcc0d8d31e184ce85fc563ba..65e04af37771a6f2ff50e8cfffc55b0aab24c6e6 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,32 @@
 Modifications for 1.1.5:
 ======================================================================
 
+* Patch by Stefan Roese, 1 Mar 2002:
+  - Added ORSG board
+  - crc32 command extended - optionally write CRC to memory
+  - CFG_DEVICE_NULLDEV for nulldev added
+
+* Patch by Rich Ireland, 01 Mar 2002:
+  add "disassemble" target
+
+* Patch by Rich Ireland, 26 Feb 2002:
+  enable RAM exceptions for the 74xx_7xx
+
+* 2 patches by Stefan Roese, 26 Feb 2002:
+  - esd boards: flash code updated (AMD 29LV320B/T added)
+  - DU405 board: FPGA updated for new revision and RTC support added
+  - 405gp_pci.c: Bug fixed in PCI configuration (Andrew May)
+  - mc146818.c: support for memory mapped RTC added
+
+  - 405gp_enet.c: rx and tx buffer descriptors now allocated (no
+    fixed address used anymore), and some code cleanup
+  - 405gp_pci.c: Removed PCI class code init for CPCI405 board
+
+* Patch by Tom Angert, 25 Feb 2002:
+  - Fix dependency of ELF loader on network support
+  - allow offset into the first flash before a JFFS2 filesystem
+  - fix idle bits in miiphybb.c
+  
 * Add support for Windriver ppmc8260 board
   Note: this flash driver uses Common Flash Interface to determine
   the geometry of the flash chips!

diff --git a/Makefile b/Makefile
index 7bc9f1ccb802dda3530df8f0453099625d281c6c..1c103292a4e22a78d70b777b3223d1361e699d4e 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -103,6 +103,9 @@ ppcboot.srec:       ppcboot
 ppcboot.bin:   ppcboot
                $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
 
+ppcboot.dis:   ppcboot
+               $(OBJDUMP) -d $< > $@
+
 ppcboot:       depend subdirs $(OBJS) $(LDSCRIPT)
                $(LD) $(LDFLAGS) $(OBJS) -Map ppcboot.map -o ppcboot
 
@@ -529,11 +532,12 @@ MIP405_config:unconfig
        echo "VENDOR = mpl"     >>config.mk ;   \
        echo "#include <config_$(@:_config=).h>" >config.h
 
-OCRTC_config:  unconfig
-       @echo "Configuring for $(@:_config=) Board..." ; \
+OCRTC_config           \
+ORSG_config:   unconfig
+       @echo "Configuring for $(call xtract,$@) Board..." ; \
        cd ./include ;                          \
        echo "ARCH  = ppc"      > config.mk ;   \
-       echo "BOARD = ocrtc">>config.mk ;       \
+       echo "BOARD = ocrtc"    >>config.mk ;   \
        echo "CPU   = ppc4xx"   >>config.mk ;   \
        echo "VENDOR = esd"     >>config.mk ;   \
        echo "#include <config_$(@:_config=).h>" >config.h

diff --git a/board/esd/common/flash.c b/board/esd/common/flash.c
index e6b5fa07cebc9c5e3265d431dda2af24b916cee7..63b9cf771e0c569f0f84cb499e0e4ae8c2d9bdc3 100644 (file)
--- a/board/esd/common/flash.c
+++ b/board/esd/common/flash.c
@@ -46,6 +46,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
                info->start[i] = base + (i * 0x00010000);
         } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
                   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+                  ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
                   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
                /* set sector offsets for bottom boot block type        */
                for (i=0; i<8; ++i) {           /*  8 x 8k boot sectors */
@@ -59,6 +60,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
                }
         } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
                   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+                  ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
                   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
                /* set sector offsets for top boot block type           */
                base += info->size;
@@ -131,6 +133,10 @@ void flash_print_info  (flash_info_t *info)
                                break;
        case FLASH_AM160T:      printf ("AM29LV160T (16 Mbit, top boot sector)\n");
                                break;
+       case FLASH_AM320T:      printf ("AM29LV320T (32 M, top sector)\n");
+                               break;
+       case FLASH_AM320B:      printf ("AM29LV320B (32 M, bottom sector)\n");
+                               break;
        case FLASH_AMDL322T:    printf ("AM29DL322T (32 M, top sector)\n");
                                break;
        case FLASH_AMDL322B:    printf ("AM29DL322B (32 M, bottom sector)\n");
@@ -275,6 +281,16 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
                info->size = 0x00200000;
                break;                          /* => 2 MB              */
 
+       case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+               info->flash_id += FLASH_AM320T;
+               info->sector_count = 71;
+               info->size = 0x00400000;  break;        /* => 4 MB      */
+
+       case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+               info->flash_id += FLASH_AM320B;
+               info->sector_count = 71;
+               info->size = 0x00400000;  break;        /* => 4 MB      */
+
        case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
                info->flash_id += FLASH_AMDL322T;
                info->sector_count = 71;
@@ -325,6 +341,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
                info->start[i] = base + (i * 0x00010000);
         } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322B) ||
                   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323B) ||
+                  ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
                   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324B)) {
                /* set sector offsets for bottom boot block type        */
                for (i=0; i<8; ++i) {           /*  8 x 8k boot sectors */
@@ -338,6 +355,7 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
                }
         } else if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL322T) ||
                   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL323T) ||
+                  ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ||
                   ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMDL324T)) {
                /* set sector offsets for top boot block type           */
                base += info->size;

diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c
index 660741c1cf3184f7359a7b1390d35f513e7b6436..abb858475ac1c755135d94148fdacf09b82f1c93 100644 (file)
--- a/board/esd/du405/du405.c
+++ b/board/esd/du405/du405.c
@@ -150,12 +150,11 @@ int checkboard (void)
     unsigned char str[64];
     int i = getenv_r ("serial#", str, sizeof(str));
 
-    if (!i || strncmp(str, "DU405", 5)) {
-       printf ("### No HW ID - assuming DU405\n");
-       return (1);
+    if (i == -1) {
+       printf ("### No HW ID - assuming DU405");
     }
-
-    puts(str);
+    else
+      puts(str);
 
     puts("\nFPGA:  ");
 

diff --git a/board/esd/du405/fpgadata.c b/board/esd/du405/fpgadata.c
index 499f8dc406280d23f80ee3521cd551228ff01704..fd80d2cd86043b2cf17d35b4359e59630939ffc2 100644 (file)
--- a/board/esd/du405/fpgadata.c
+++ b/board/esd/du405/fpgadata.c
@@ -1,701 +1,703 @@
  0x00,0x09,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x0f,0xf0,0x00,0x00,0x01,0x61,0x00,0x0d,
  0x64,0x75,0x72,0x61,0x67,0x34,0x30,0x35,0x2e,0x6e,0x63,0x64,0x00,0x62,0x00,0x0b,
  0x73,0x32,0x30,0x78,0x6c,0x74,0x71,0x31,0x34,0x34,0x00,0x63,0x00,0x0b,0x32,0x30,
- 0x30,0x31,0x2f,0x31,0x31,0x2f,0x31,0x39,0x00,0x64,0x00,0x09,0x31,0x36,0x3a,0x32,
- 0x33,0x3a,0x34,0x34,0x00,0x65,0xe2,0x01,0x00,0x00,0x2b,0x7b,0xff,0x30,0xe6,0xe5,
- 0xe5,0x02,0x04,0x01,0xe6,0x04,0x01,0x0c,0x03,0x01,0x01,0x05,0x01,0x01,0x05,0x01,
- 0x01,0x01,0x07,0x01,0x07,0x02,0x06,0x07,0x02,0x01,0x06,0x02,0x04,0x04,0x02,0x01,
- 0x01,0x09,0x01,0x05,0x01,0x01,0x01,0x07,0x02,0x02,0x03,0x05,0x01,0x01,0x01,0x03,
- 0x01,0x03,0x07,0x02,0x06,0x05,0x03,0x01,0x07,0x09,0x01,0x0d,0x09,0x03,0x05,0x03,
- 0x05,0x09,0x09,0x03,0x05,0x03,0x09,0x11,0x09,0x03,0x05,0x09,0x09,0x03,0x03,0x01,
- 0x09,0x09,0x09,0x03,0x05,0x09,0x12,0xe6,0x13,0x03,0x05,0x03,0x05,0x17,0x2d,0x05,
- 0x03,0x01,0x03,0x02,0x02,0x0d,0x05,0x03,0x02,0x02,0x0b,0x0b,0x03,0x08,0x0a,0x0b,
- 0xe8,0x0e,0x07,0xe6,0x06,0xe6,0x08,0x09,0x09,0x09,0x09,0x09,0x04,0x04,0x09,0xe6,
- 0x06,0xe6,0x08,0x09,0x06,0xe7,0x08,0x09,0x09,0x09,0x09,0x0e,0x03,0x14,0xe5,0xe6,
- 0x04,0xe5,0xe6,0x04,0xe5,0x07,0x09,0x03,0x05,0x09,0xe5,0x01,0x05,0x03,0x05,0x09,
- 0xe5,0x02,0xe5,0x04,0xe5,0xe6,0x04,0xe5,0x07,0x03,0x05,0xe8,0x04,0xe5,0x07,0xe5,
- 0x07,0x03,0x05,0x09,0x09,0x09,0x01,0xe6,0x98,0x01,0x44,0xe6,0xe5,0x14,0x09,0x51,
- 0x09,0x1d,0x43,0x02,0x17,0x09,0x4f,0x28,0xe5,0x42,0xe7,0x30,0x09,0x09,0x01,0x11,
- 0x02,0x14,0x1b,0x27,0x28,0x01,0x01,0x74,0x09,0x60,0xe7,0xe5,0x0a,0xe5,0x37,0x3f,
- 0xe5,0x54,0xe5,0xe6,0x0c,0x63,0x15,0x57,0xe5,0xe5,0x5a,0x15,0x4f,0x1d,0xe7,0x0f,
- 0x09,0x09,0x09,0x09,0x01,0x07,0xe5,0x07,0x09,0x09,0x09,0x0b,0x09,0x09,0x09,0x09,
- 0x09,0x09,0x09,0x09,0x09,0x08,0x08,0x10,0x09,0x09,0x09,0x09,0x01,0x07,0x09,0x09,
- 0x04,0x04,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0xe6,0xe5,
- 0x0c,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0x07,0xe5,0x07,
- 0xe5,0x07,0xe5,0x07,0xe5,0x07,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,
- 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x04,0x02,0xe5,0x0f,0x02,0x10,0x08,
- 0x09,0x0a,0x09,0x08,0x0a,0x09,0x09,0x09,0x06,0x03,0x09,0x0a,0x08,0x05,0x03,0x0a,
- 0x09,0x08,0x0a,0x09,0x0d,0xe5,0xe6,0x05,0x06,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
- 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x05,0x01,0xe5,0x07,0xe5,0x09,0xe5,0x07,
+ 0x30,0x32,0x2f,0x30,0x32,0x2f,0x32,0x31,0x00,0x64,0x00,0x09,0x31,0x32,0x3a,0x35,
+ 0x31,0x3a,0x30,0x38,0x00,0x65,0xe2,0x01,0x00,0x00,0x2b,0x98,0xff,0x30,0xe6,0xe5,
+ 0xe5,0x02,0x04,0x01,0xe6,0x04,0x01,0x0d,0x04,0x04,0x02,0x01,0x04,0x04,0x03,0x07,
+ 0x01,0x03,0x01,0x04,0x11,0x01,0x06,0x02,0x15,0x09,0x02,0x05,0x07,0x02,0x02,0x01,
+ 0x09,0x03,0x07,0x01,0x03,0x01,0x0b,0x05,0x03,0x01,0x07,0x08,0xe5,0xe5,0x24,0x05,
+ 0x09,0x11,0x01,0x03,0x03,0x05,0x0d,0x09,0x0b,0x09,0x01,0x1d,0x09,0x13,0x03,0x05,
+ 0x12,0xe6,0x11,0x01,0x03,0x02,0x02,0x03,0x03,0x01,0x15,0x01,0x02,0x28,0x01,0x05,
+ 0x02,0xe5,0xe5,0x02,0x02,0x02,0x0d,0x02,0x02,0x03,0x02,0xe5,0xe5,0x14,0x01,0x02,
+ 0xe5,0x12,0x0b,0x03,0x0f,0x09,0x09,0x09,0x09,0x09,0x04,0x01,0x02,0x06,0x02,0x09,
+ 0x06,0xe7,0x05,0x04,0x06,0x02,0x06,0x02,0x09,0x07,0xe6,0x08,0x09,0x07,0xe6,0x08,
+ 0x09,0x0e,0xe5,0xe6,0x0d,0x05,0xe5,0x01,0x05,0xe5,0x01,0x05,0xe5,0x07,0x09,0xe5,
+ 0x01,0x05,0xe5,0x07,0xe6,0xe5,0x04,0x03,0x05,0xe8,0x04,0xe6,0x02,0x05,0xe6,0xe5,
+ 0x04,0xe6,0x06,0x03,0x05,0xe5,0xe6,0x04,0xe5,0x07,0x09,0xe5,0xe6,0x04,0x09,0x09,
+ 0x09,0xe8,0x46,0x09,0x14,0xe5,0x06,0x0b,0x09,0x15,0x1d,0x24,0x02,0xe5,0xe5,0x45,
+ 0x08,0x15,0x33,0x1d,0x28,0x70,0xe5,0x09,0x09,0x14,0x42,0x02,0xe5,0x30,0x27,0x01,
+ 0x15,0x1b,0x1d,0x32,0x01,0x01,0x5b,0x0c,0x51,0x24,0x01,0xe5,0xe5,0x28,0xe5,0x1c,
+ 0x25,0x53,0x19,0xe5,0x01,0x2b,0x45,0x6c,0xe5,0xe6,0x35,0x09,0x07,0x01,0x09,0x09,
+ 0x12,0x63,0x09,0x02,0x03,0x0c,0x09,0x09,0x09,0x09,0x09,0x09,0x07,0x01,0x09,0x01,
+ 0x07,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0x02,0xe5,0x02,0x0c,
+ 0x09,0x09,0x09,0x06,0x02,0x05,0xe5,0x01,0x07,0x01,0x05,0x03,0x07,0x01,0x09,0x0b,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0d,0xe5,0x01,0x05,0x07,0xe5,0x05,
+ 0x01,0xe5,0x07,0xe5,0x07,0xe5,0x07,0x03,0x05,0xe5,0x07,0x09,0xe5,0x07,0x09,0xe5,
+ 0x07,0x01,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x04,0x02,0xe5,0x12,0x04,0x0b,0x05,0x02,0xe5,0x07,0xe5,0x08,0x09,
+ 0x08,0xe5,0x08,0x09,0x09,0x09,0x06,0x03,0xe5,0x07,0xe5,0x08,0x08,0xe5,0x07,0xe5,
+ 0x08,0x09,0x04,0x03,0xe5,0x08,0x09,0x0d,0x01,0xe6,0x05,0x06,0xe5,0x07,0xe5,0xe5,
+ 0x05,0xe5,0xe5,0x01,0x03,0xe5,0x14,0x06,0x09,0x13,0xe5,0x09,0xe5,0xe5,0x05,0xe5,
+ 0xe5,0x05,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0x07,0xe5,0x07,0xe5,0xe5,
+ 0x05,0xe5,0x07,0xe5,0x07,0x02,0x03,0xe8,0x0e,0x01,0x09,0x09,0x07,0x08,0xe5,0x07,
+ 0x09,0xe5,0x07,0xe5,0x07,0xe5,0x08,0x01,0x0b,0x09,0x07,0x0b,0x09,0x07,0x09,0x13,
+ 0x09,0x0e,0x02,0xe5,0x0c,0x09,0x03,0x05,0x09,0x12,0x09,0xe5,0x08,0x13,0x09,0x01,
+ 0x09,0x09,0x09,0x09,0x09,0x09,0x07,0x01,0x09,0x09,0x10,0xe8,0x03,0x08,0x02,0x03,
+ 0x02,0x02,0x06,0x02,0x03,0x02,0x02,0x06,0x02,0x09,0x06,0x02,0x06,0x02,0x06,0x02,
+ 0x06,0x02,0x04,0x01,0x01,0x02,0x06,0x02,0x06,0x02,0x06,0x02,0xe5,0x04,0x02,0x06,
+ 0x02,0x06,0x02,0x06,0x02,0x03,0x02,0x02,0x06,0x02,0x0d,0x01,0x01,0x03,0xe5,0x09,
+ 0x09,0x09,0xe5,0x0f,0xe5,0x25,0x0b,0x04,0xe5,0x01,0x02,0x06,0x02,0x13,0x09,0x36,
+ 0x0d,0x23,0x35,0x82,0x01,0x03,0x10,0x09,0x02,0x06,0x11,0x09,0x1c,0xe5,0x0a,0x03,
+ 0xe6,0xe5,0x02,0x03,0x05,0x0d,0x05,0x03,0x05,0x17,0x27,0x02,0xe5,0x29,0x50,0x27,
+ 0x11,0x28,0xe5,0x01,0x10,0x09,0x09,0x09,0x09,0x04,0x04,0xe5,0x07,0xe5,0x07,0x09,
+ 0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0e,0xe7,0x0e,0xe5,0x02,
+ 0x02,0x02,0x06,0x02,0x10,0xe5,0xe5,0x38,0x1e,0x06,0x02,0x13,0x01,0xe5,0x2c,0xe6,
+ 0x17,0x09,0x06,0x09,0x01,0x10,0x19,0x24,0x13,0x13,0x02,0x11,0x16,0x05,0x02,0x03,
+ 0x01,0x10,0xe5,0x08,0x70,0x09,0x3f,0x01,0x02,0xe5,0x02,0x26,0x11,0x09,0x28,0x02,
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+ 0x5f,0x0e,0x01,0x01,0x2d,0x97,0x08,0xe5,0x0d,0xe5,0x01,0x09,0x23,0x44,0x52,0x08,
+ 0x11,0xe6,0x02,0x0b,0xe5,0x01,0x06,0x06,0xe7,0x07,0xe5,0x05,0xe7,0x05,0xe7,0x05,
+ 0xe7,0xe5,0x05,0xe5,0x08,0x08,0xe5,0x09,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,
+ 0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x0b,0x02,0xe6,0x0d,0x01,
+ 0x02,0x04,0x01,0x02,0x04,0x01,0x02,0x04,0x01,0x07,0x01,0x07,0x01,0x02,0x02,0x01,
+ 0x01,0x08,0xe5,0x0d,0x02,0x01,0x0b,0x09,0x09,0x09,0x07,0x01,0x01,0xe5,0x05,0x09,
+ 0x09,0x02,0x06,0x09,0x0d,0x02,0xe5,0x0f,0x08,0x13,0x09,0x1d,0x09,0x04,0x04,0x08,
+ 0x02,0x04,0x04,0x09,0x04,0x04,0x09,0x09,0x09,0x09,0x09,0x09,0x0f,0x02,0x14,0x41,
+ 0x87,0x01,0xe6,0x18,0x03,0x05,0x09,0x09,0x09,0x09,0x09,0x13,0x0b,0x09,0x04,0x04,
+ 0x09,0x04,0x04,0x02,0x06,0x09,0x09,0x09,0x09,0x0e,0x01,0x01,0x0d,0xe5,0x07,0xe6,
+ 0x06,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe6,0x06,0xe6,0x06,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x01,0x03,0x03,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,0x07,0xe5,
+ 0x07,0xe5,0x07,0xe5,0x07,0xe5,0x0e,0xe8,0x02,0x05,0x03,0x09,0x01,0x04,0x02,0x01,
+ 0x07,0x09,0x09,0x01,0x07,0x01,0x07,0x09,0x07,0x01,0x0b,0x09,0x09,0x09,0x09,0x09,
+ 0x09,0x09,0x09,0x09,0x14,0x0e,0x09,0x09,0x09,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0x09,
+ 0x09,0xe5,0xe5,0x05,0x09,0xe5,0xe5,0x07,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,
+ 0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,0xe5,0xe5,0x05,
+ 0xe5,0xe5,0x05,0xe5,0xe5,0x0f,0x0e,0x09,0x01,0x07,0x09,0x09,0x09,0x09,0x09,0x09,
+ 0x01,0x07,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0f,0x01,0xe6,0x47,
+ 0x11,0x76,0x0c,0x01,0x01,0x0e,0x05,0x03,0x05,0x03,0x09,0x05,0x03,0x09,0x09,0x09,
+ 0x09,0x09,0x06,0x01,0x02,0x05,0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0f,
+ 0xe8,0x0f,0x13,0x1d,0x09,0x24,0x70,0x10,0x09,0x09,0x09,0x09,0x09,0x09,0x05,0x03,
+ 0x09,0x09,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x0e,0x01,0xe5,0x46,
+ 0x96,0x02,0xe5,0x70,0x6e,0x01,0x22,0x1d,0x09,0x13,0x11,0xe5,0x67,0x06,0xe5,0x06,
+ 0x06,0x06,0x02,0x06,0x02,0x06,0x16,0x06,0x02,0x13,0x06,0x79,0xe5,0xe5,0x3a,0x1d,
+ 0x33,0x1d,0x09,0x2a,0xe6,0x06,0x05,0x08,0xe5,0x07,0xe5,0x07,0x14,0x08,0xe5,0x12,
+ 0x08,0x0a,0x65,0x06,0x03,0x71,0x66,0x05,0xe5,0xe6,0xdd,0xe5,0xe6,0x0c,0xe5,0x04,
+ 0xe8,0x04,0xe8,0x04,0xe6,0x06,0x09,0x02,0xe5,0x04,0xe8,0x04,0x09,0x02,0xe5,0x04,
+ 0xe6,0x06,0x0b,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x01,0xe6,0x0c,
+ 0xe6,0x05,0xe7,0x05,0xe7,0x05,0x01,0xe5,0x08,0x07,0xe6,0x05,0xe7,0x08,0x07,0xe6,
+ 0x05,0x02,0x07,0x03,0x09,0x09,0x09,0x09,0x09,0x09,0x09,0x08,0xe5,0x07,0xe5,0x0e,
+ 0xe5,0xe5,0x33,0x2d,0x0e,0x10,0x13,0x48,0x02,0x11,0x03,0x05,0x03,0x05,0x03,0x05,
+ 0x03,0x01,0x0d,0x03,0x05,0x03,0x01,0x0d,0x03,0x01,0x03,0x07,0x09,0x09,0x09,0x09,
+ 0x03,0x05,0x09,0x09,0x11,0x13,0x01,0xe5,0x0a,0x06,0x09,0x09,0x04,0x01,0x02,0x01,
+ 0x03,0x07,0x05,0x09,0x01,0x03,0x07,0x0e,0xe5,0x02,0x06,0xe5,0x02,0x04,0x04,0x01,
+ 0x07,0x04,0x04,0x05,0x03,0x01,0x07,0x01,0x07,0x01,0x03,0x03,0x02,0x04,0x04,0x06,
+ 0x01,0x03,0xe5,0xe5,0xe6,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
+ 0xff,0xff,0xff,0xff,

diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c
index c05f0cea0a1b7bd272a8e7e7b3f03067863ec013..28ac7193400b625f3021875c9aae9ef161abd1c4 100644 (file)
--- a/board/esd/ocrtc/flash.c
+++ b/board/esd/ocrtc/flash.c
@@ -45,6 +45,7 @@ unsigned long flash_init (void)
        int i;
         uint pbcr;
         unsigned long base_b0, base_b1;
+       int size_val;
 
        /* Init: no FLASHes known */
        for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
@@ -70,7 +71,20 @@ unsigned long flash_init (void)
             pbcr = mfdcr(ebccfgd);
             mtdcr(ebccfga, pb0cr);
             base_b1 = -size_b1;
-            pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
+           switch (size_b1)
+             {
+               case 1<<20:
+                 size_val = 0; break;
+               case 2<<20:
+                 size_val = 1; break;
+               case 4<<20:
+                 size_val = 2; break;
+               case 8<<20:
+                 size_val = 3; break;
+               case 16<<20:
+                 size_val = 4; break;
+             }
+            pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val<<17);
             mtdcr(ebccfgd, pbcr);
             //          printf("pb1cr = %x\n", pbcr);
           }
@@ -81,7 +95,20 @@ unsigned long flash_init (void)
             pbcr = mfdcr(ebccfgd);
             mtdcr(ebccfga, pb1cr);
             base_b0 = base_b1 - size_b0;
-            pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
+           switch (size_b1)
+             {
+               case 1<<20:
+                 size_val = 0; break;
+               case 2<<20:
+                 size_val = 1; break;
+               case 4<<20:
+                 size_val = 2; break;
+               case 8<<20:
+                 size_val = 3; break;
+               case 16<<20:
+                 size_val = 4; break;
+             }
+            pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val<<17);
             mtdcr(ebccfgd, pbcr);
             //            printf("pb0cr = %x\n", pbcr);
           }

diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c
index 39adc6884db78f28190af8899e4e1e9053528567..f756f61544ce6bb59bac2bc81c7429b1a9f9bdda 100644 (file)
--- a/board/esd/ocrtc/ocrtc.c
+++ b/board/esd/ocrtc/ocrtc.c
@@ -52,6 +52,12 @@ int board_pre_init (void)
   mtdcr(uicvcr, 0x00000001);       /* set vect base=0,INT0 highest priority*/
   mtdcr(uicsr, 0xFFFFFFFF);        /* clear all ints */
 
+  /*
+   * EBC Configuration Register: clear EBTC -> high-Z ebc signals between
+   * transfers, set device-paced timeout to 256 cycles
+   */
+  mtebc(epcr, 0x20400000);
+ 
   return 0;
 }
 
@@ -70,24 +76,19 @@ int misc_init_f(void)
 
 int checkboard (void)
 {
-    unsigned char *s = getenv("serial#");
-    unsigned char *e;
+    unsigned char str[64];
+    int i = getenv_r ("serial#", str, sizeof(str));
 
-    if (!s)
-      {
-       printf ("### No HW ID - assuming OCRTC");
-      }
+    if (i == -1) {
+#ifdef CONFIG_OCRTC
+       printf ("### No HW ID - assuming OCRTC");
+#endif
+#ifdef CONFIG_ORSG
+       printf ("### No HW ID - assuming ORSG");
+#endif
+    }
     else
-      {
-        for (e=s; *e; ++e) {
-          if (*e == ' ')
-           break;
-        }
-
-        for ( ; s<e; ++s) {
-          putc (*s);
-        }
-      }
+      puts(str);
 
     putc ('\n');
 

diff --git a/common/cmd_elf.c b/common/cmd_elf.c
index 850818987c04b18a296a3b15b30618105bb1d07d..a399a0b6ba3a337f239bbcec1afbdd6bf186b0b1 100644 (file)
--- a/common/cmd_elf.c
+++ b/common/cmd_elf.c
@@ -100,6 +100,7 @@ int do_bootvx (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
                return 1;
        }
 
+#if (CONFIG_COMMANDS & CFG_CMD_NET)
        /* Check to see if we need to tftp the image ourselves before starting */
 
        if ((argc == 2) && (strcmp (argv[1], "tftp") == 0)) {
@@ -107,6 +108,7 @@ int do_bootvx (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
                        return 1;
                printf ("Automatic boot of VxWorks image at address 0x%08lx ... \n", addr);
        }
+#endif
 
        /* This should equate
         * to NV_RAM_ADRS + NV_BOOT_OFFSET + NV_ENET_OFFSET

diff --git a/common/cmd_jffs2.c b/common/cmd_jffs2.c
index 7dba497b46792928875949f99fff7c56c1673ae6..e041e6152fd75a14954d680277eea8b67a2557f0 100644 (file)
--- a/common/cmd_jffs2.c
+++ b/common/cmd_jffs2.c
@@ -43,12 +43,22 @@ get_part_info(struct part_info *part)
        int i;
 
        memset(part, 0, sizeof(*part));
+#if defined(CFG_JFFS2_FIRST_SECTOR)
+       part->offset = (unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR];
+#else
        part->offset = (unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[0];
+#endif
 
        /* Figure out flash partition size */
        for (i = CFG_JFFS2_FIRST_BANK; i < CFG_JFFS2_NUM_BANKS+CFG_JFFS2_FIRST_BANK; i++) 
            part->size += flash_info[i].size;
 
+#if defined(CFG_JFFS2_FIRST_SECTOR) && (CFG_JFFS2_FIRST_SECTOR > 0)
+       part->size -= 
+            flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR] - 
+            flash_info[CFG_JFFS2_FIRST_BANK].start[0];
+#endif
+
        /* unused in current jffs2 loader */
        part->erasesize = 0;
 }

diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index 82b6cb8f0b2b6b1dcd6075a73d90d17311857997..140bff21cedeb6e3a339058331bbccf82ff689af 100644 (file)
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -598,10 +598,12 @@ mod_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
        mm_last_size = size;
        return 0;       
 }
+
 int do_mem_crc (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 {
        ulong   addr, length;
        ulong   crc;
+       ulong   *ptr;
 
        if (argc < 3) {
                printf ("Usage:\n%s\n", cmdtp->usage);
@@ -617,6 +619,13 @@ int do_mem_crc (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
 
        printf ("CRC32 for %08lx ... %08lx ==> %08lx\n",
                addr, addr + length -1, crc);
+
+       if (argc > 3)
+         {
+           ptr = (ulong *)simple_strtoul(argv[3], NULL, 16);
+           *ptr = crc;
+         }
+
        return 0;                               
 }
 

diff --git a/common/devices.c b/common/devices.c
index 89f3b79f99d8b973fe0771920defb27d852670e1..d21438b94a60a1f725cb92b1a34841006b0c1619 100644 (file)
--- a/common/devices.c
+++ b/common/devices.c
@@ -32,36 +32,64 @@ list_t devlist = 0;
 device_t *stdio_devices[] = { NULL, NULL, NULL };
 char *stdio_names[MAX_FILES] = { "stdin", "stdout", "stderr" };
 
+#ifdef CFG_DEVICE_NULLDEV
+void nulldev_putc(const char c)
+{
+  /* nulldev is empty! */
+}
+
+void nulldev_puts(const char *s)
+{
+  /* nulldev is empty! */
+}
+
+int nulldev_input(void)
+{
+  /* nulldev is empty! */
+  return 0;
+}
+#endif
+
 /**************************************************************************
  * SYSTEM DRIVERS
  **************************************************************************
  */
 
-static int drv_system_init (void)
+static void drv_system_init (void)
 {
-       int error, devices = 1;
-       device_t serdev;
+       device_t dev;
 
-       memset (&serdev, 0, sizeof (serdev));
+       memset (&dev, 0, sizeof (dev));
 
-       strcpy (serdev.name, "serial");
-       serdev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+       strcpy (dev.name, "serial");
+       dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
 #if CONFIG_SERIAL_SOFTWARE_FIFO
        serial_buffered_init ();
-       serdev.putc = serial_buffered_putc;
-       serdev.puts = serial_buffered_puts;
-       serdev.getc = serial_buffered_getc;
-       serdev.tstc = serial_buffered_tstc;
+       dev.putc = serial_buffered_putc;
+       dev.puts = serial_buffered_puts;
+       dev.getc = serial_buffered_getc;
+       dev.tstc = serial_buffered_tstc;
 #else
-       serdev.putc = serial_putc;
-       serdev.puts = serial_puts;
-       serdev.getc = serial_getc;
-       serdev.tstc = serial_tstc;
+       dev.putc = serial_putc;
+       dev.puts = serial_puts;
+       dev.getc = serial_getc;
+       dev.tstc = serial_tstc;
 #endif
 
-       error = device_register (&serdev);
+       device_register (&dev);
 
-       return (error == 0) ? devices : error;
+#ifdef CFG_DEVICE_NULLDEV
+       memset (&dev, 0, sizeof (dev));
+
+       strcpy (dev.name, "nulldev");
+       dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
+       dev.putc = nulldev_putc;
+       dev.puts = nulldev_puts;
+       dev.getc = nulldev_input;
+       dev.tstc = nulldev_input;
+
+       device_register (&dev);
+#endif
 }
 
 /**************************************************************************

diff --git a/common/miiphybb.c b/common/miiphybb.c
index 3328aeabfff2e114c1cb731f6c4c2e4f930949f3..83d0504b43010a46365919edb91308b9fd4aba1a 100644 (file)
--- a/common/miiphybb.c
+++ b/common/miiphybb.c
@@ -52,6 +52,7 @@ static void miiphy_pre(char         read,
    * error.  This means that we are doing more preambles than we need,
    * but it is safer and will be much more robust.
    */
+
   MDIO_ACTIVE;
   MDIO(1);
   for(j = 0; j < 32; j++)
@@ -134,6 +135,13 @@ int miiphy_read(unsigned char  addr,
   if(MDIO_READ != 0)
   {
     /* printf("PHY didn't drive TA low\n"); */
+    for(j = 0; j < 32; j++)
+    {
+      MDC(0);
+      MIIDELAY;
+      MDC(1);
+      MIIDELAY;
+    }
     return(-1);
   }
 
@@ -152,6 +160,13 @@ int miiphy_read(unsigned char  addr,
     MIIDELAY;
   }
 
+  MDC(1);
+  MIIDELAY;
+  MDC(0);
+  MIIDELAY;
+  MDC(1);
+  MIIDELAY;
+
   *value = rdreg;
 
 #ifdef DEBUG
@@ -204,6 +219,10 @@ int miiphy_write(unsigned char  addr,
    * Tri-state the MDIO line.
    */
   MDIO_TRISTATE;
+  MDC(0);
+  MIIDELAY;
+  MDC(1);
+  MIIDELAY;
 
   return 0;
 }

diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S
index 694fe9cfe63e4ded8569988712e6dcbb6dae7701..66196505367e63d43c1512ddece59ea09ab03b71 100644 (file)
--- a/cpu/74xx_7xx/start.S
+++ b/cpu/74xx_7xx/start.S
@@ -245,7 +245,7 @@ _back:
        .globl  _end_of_vectors
 _end_of_vectors:
 
-       . = 0x2000
+       . = 0x3000
 
 boot_cold:
 boot_warm:
@@ -802,6 +802,11 @@ trap_init:
        cmplw   0, r7, r8
        blt     4b
 
+       /* enable execptions from RAM vectors */
+       mfmsr   r7
+       li              r8,MSR_IP
+       andc    r7,r7,r8
+       mtmsr   r7
 
        mtlr    r4                      /* restore link register        */
        blr

diff --git a/cpu/ppc4xx/405gp_enet.c b/cpu/ppc4xx/405gp_enet.c
index 92cf72bc3788fcf6dfd63568153bf47eb17d4d42..1b5658e1ce26116a9a363f3b396f205d9d0ad6e8 100644 (file)
--- a/cpu/ppc4xx/405gp_enet.c
+++ b/cpu/ppc4xx/405gp_enet.c
@@ -61,6 +61,9 @@
   |              - Wait for PHY auto negotiation to complete added
   |  06-Feb-02   stefan.roese@esd-electronics.com
   |              - Bug fixed in waiting for auto negotiation to complete
+  |  26-Feb-02   stefan.roese@esd-electronics.com
+  |              - rx and tx buffer descriptors now allocated (no fixed address
+  |                used anymore)
   +-----------------------------------------------------------------------------*/
 
 #include <ppcboot.h>
@@ -75,32 +78,9 @@
 
 #ifdef CONFIG_405GP
 
-
-#define MAXPACKET       1518
-#define ENET_MINPACKET  64
-
 #define EMAC_RESET_TIMEOUT 1000                        /* 1000 ms reset timeout */
 #define PHY_AUTONEGOTIATE_TIMEOUT 2000                 /* 2000 ms autonegotiate timeout */
 
-static __inline__ unsigned long get_msr(void)
-{
-  unsigned long msr;
-
-  asm volatile("mfmsr %0" : "=r" (msr) :);
-  return msr;
-}
-
-static __inline__ void set_msr(unsigned long msr)
-{
-  asm volatile("mtmsr %0" : : "r" (msr));
-}
-
-/*-----------------------------------------------------------------------------+
-| Defines for number of buffers and their starting addresses.
-| Buffers are in SDRAM space and must be above 0xA000 to avoid conflict
-| with the ROM Monitor's data section and must be below 0xF000, where
-| the buffers for an PCI ethernet device (if present) would start.
-+-----------------------------------------------------------------------------*/
 #define NUM_TX_BUFF 1
 /* AS.HARNOIS
  * Use PKTBUFSRX (include/net.h) instead of setting NUM_RX_BUFF again
@@ -109,10 +89,6 @@ static __inline__ void set_msr(unsigned long msr)
  */
 #define NUM_RX_BUFF PKTBUFSRX
 
-
-#define TX_BUF_START 0x0000A000
-#define RX_BUF_START 0x0000A800
-
 /* Ethernet Transmit and Receive Buffers */
 /* AS.HARNOIS
  * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
@@ -123,21 +99,6 @@ static __inline__ void set_msr(unsigned long msr)
 
 static char *txbuf_ptr;
 
-/*-----------------------------------------------------------------------------+
-| Defines for TX and RX descriptors.
-| IMPORTANT: The descriptors should be placed in NON-CACHEABLE memory since
-|            they are 8 bytes each and must be contiguous. If they were
-|            placed in cacheable memory, maintaining software cache coherency
-|            may not be possible as a cache flush of a single descriptor could
-|            corrupt the other three (in real memory) that are within the same
-|            cache line. Here we use the SRAM on the board for the descriptors.
-|            The 405GP reference board has 512K of SRAM. The first
-|            0x1000 bytes should be reserved for this driver.
-+-----------------------------------------------------------------------------*/
-#define EMAC_TX_DESCRIPTOR_ADDR 0x00ef0000
-#define EMAC_RX_DESCRIPTOR_ADDR (EMAC_TX_DESCRIPTOR_ADDR + \
-                                (4 * NUM_TX_BUFF * sizeof(mal_desc_t)))
-
 /* define the number of channels implemented */
 #define EMAC_RXCHL      1
 #define EMAC_TXCHL      1
@@ -248,8 +209,8 @@ int eth_init (bd_t *bis)
   unsigned mode_reg;
   unsigned short reg_short;
 
-  msr = get_msr();
-  set_msr(msr & ~(MSR_EE));          /* disable interrupts */
+  msr = mfmsr();
+  mtmsr(msr & ~(MSR_EE));          /* disable interrupts */
 
 #ifdef INFO_405_ENET
   /* AS.HARNOIS
@@ -330,8 +291,11 @@ int eth_init (bd_t *bis)
   mtdcr(malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
 
   /* set up the TX and RX descriptors */
-  tx = (mal_desc_t *) EMAC_TX_DESCRIPTOR_ADDR;
-  rx = (mal_desc_t *) EMAC_RX_DESCRIPTOR_ADDR;
+  if (first_init == 0)
+    {
+      tx = (mal_desc_t *)malloc(4 * NUM_TX_BUFF * sizeof(mal_desc_t));
+      rx = (mal_desc_t *)malloc(4 * NUM_RX_BUFF * sizeof(mal_desc_t));
+    }
 
   for (i = 0; i < NUM_TX_BUFF; i++)
     {
@@ -385,8 +349,8 @@ int eth_init (bd_t *bis)
   out32 (EMAC_IAL, reg);
 
   /* setup MAL tx & rx channel pointers */
-  mtdcr(maltxctp0r, EMAC_TX_DESCRIPTOR_ADDR);
-  mtdcr(malrxctp0r, EMAC_RX_DESCRIPTOR_ADDR);
+  mtdcr(maltxctp0r, tx);
+  mtdcr(malrxctp0r, rx);
 
   /* Reset transmit and receive channels */
   mtdcr(malrxcarr, 0x80000000);     /* 2 channels */
@@ -469,7 +433,7 @@ int eth_init (bd_t *bis)
   out32(EMAC_ISR, 0xffffffff);      /* clear pending interrupts */
   out32(EMAC_IER, emac_ier);
 
-  set_msr(msr);                     /* enable interrupts again */
+  mtmsr(msr);                     /* enable interrupts again */
 
   bis_save = bis;
   first_init = 1;
@@ -774,8 +738,8 @@ int eth_rx(void)
           break;     /* nothing received - leave for() loop */
         }
 
-      msr = get_msr();
-      set_msr(msr & ~(MSR_EE));
+      msr = mfmsr();
+      mtmsr(msr & ~(MSR_EE));
 
       length = rx[user_index].data_len;
 
@@ -795,7 +759,7 @@ int eth_rx(void)
       packetHandled++;
 #endif
 
-      set_msr(msr);                 /* Enable IRQ's */
+      mtmsr(msr);                 /* Enable IRQ's */
     }
 
   is_receiving = 0; /* tell driver */

diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 030e497efd4a40d0a36d88fcab02a53d205e6ea9..39119b9e2e2212698aa7bfba08facb62f2567682 100644 (file)
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -60,6 +60,9 @@
 |  28-Sep-01   stefan.roese@esd-electronics.com
 |              - Changed pci master configuration for linux compatibility
 |                (no need for bios_fixup() anymore)
+|  26-Feb-02   stefan.roese@esd-electronics.com
+|              - Bug fixed in pci configuration (Andrew May)
+|              - Removed pci class code init for CPCI405 board
 +----------------------------------------------------------------------------*/
 
 #include <ppcboot.h>
@@ -185,13 +188,6 @@ void pci_init(bd_t *bd)
   PCI_Write_CFG_Reg(PCIDEVID_405GP, PCISSDEVICEID, CFG_PCI_SUBSYS_DEVICEID, 2);
 #endif
 
-#ifdef CONFIG_CPCI405
-  /*
-   * Insert PCI Class Code
-   */
-  PCI_Write_CFG_Reg(PCIDEVID_405GP, PCICLASSCODE, CFG_PCI_CLASSCODE, 2);
-#endif
-
 #if 0  /* test-only: no need yet! */
   /*--------------------------------------------------------------------------+
     | If PCI speed = 66Mhz, set 66Mhz capable bit.
@@ -415,7 +411,7 @@ void    PCI_Scan(int BusNum)
 +----------------------------------------------------------------------*/
 void    PCI_Config_Device(int BusDevFunc, int NumBaseAddr)
 {
-  int     AddrSlot, i;
+  int     AddrSlot;
   unsigned long  AddrDesc, AddrProg, Min_Gnt_Val, int_line;
 
   for (AddrSlot = 0; AddrSlot < NumBaseAddr; AddrSlot++)
@@ -435,10 +431,7 @@ void    PCI_Config_Device(int BusDevFunc, int NumBaseAddr)
         {
           AddrDesc &= 0xFFFFFFF0;
 
-          for (i = 0; (AddrDesc & 1) != 1; i++)
-            AddrDesc = AddrDesc >> 1;
-
-          AddrDesc = 1 << i;
+         AddrDesc = ~AddrDesc + 1;
 
           if ((unsigned long)AddrDesc < 4096)
             AddrDesc = 4096;
@@ -454,10 +447,8 @@ void    PCI_Config_Device(int BusDevFunc, int NumBaseAddr)
         {
           AddrDesc &= 0xFFFFFFFC;
 
-          for (i = 0; (AddrDesc & 1) != 1; i++)
-            AddrDesc = AddrDesc >> 1;
+         AddrDesc = ~AddrDesc + 1;
 
-          AddrDesc = 1 << i;
 #ifdef DEBUG
           printf("  PCI I/O space = 0x%x bytes \n",AddrDesc);
 #endif
@@ -515,7 +506,7 @@ void    PCI_Config_Device(int BusDevFunc, int NumBaseAddr)
 +----------------------------------------------------------------------*/
 void    PCI_Config_VGA_Device(int BusDevFunc, int NumBaseAddr)
 {
-  int     AddrSlot, i;
+  int     AddrSlot;
   unsigned long  AddrDesc, AddrProg, Min_Gnt_Val;
 
   for (AddrSlot = 0; AddrSlot < NumBaseAddr; AddrSlot++)
@@ -535,10 +526,7 @@ void    PCI_Config_VGA_Device(int BusDevFunc, int NumBaseAddr)
         {
           AddrDesc &= 0xFFFFFFF0;
 
-          for (i = 0; (AddrDesc & 1) != 1; i++)
-            AddrDesc = AddrDesc >> 1;
-
-          AddrDesc = 1 << i;
+         AddrDesc = ~AddrDesc + 1;
 
           if ((unsigned long)AddrDesc < 4096)
             AddrDesc = 4096;
@@ -554,10 +542,8 @@ void    PCI_Config_VGA_Device(int BusDevFunc, int NumBaseAddr)
         {
           AddrDesc &= 0xFFFFFFFC;
 
-          for (i = 0; (AddrDesc & 1) != 1; i++)
-            AddrDesc = AddrDesc >> 1;
+         AddrDesc = ~AddrDesc + 1;
 
-          AddrDesc = 1 << i;
 #ifdef DEBUG
           printf("  PCI I/O space = 0x%x bytes \n",AddrDesc);
 #endif

diff --git a/include/cmd_mem.h b/include/cmd_mem.h
index c10af605a1561bbdac4c3ef1b77dc210e2fd03c6..9d96f66cd7c13a80510c05287d61f37dcbb98f00 100644 (file)
--- a/include/cmd_mem.h
+++ b/include/cmd_mem.h
@@ -62,7 +62,7 @@
 #define        CMD_TBL_CRC     MK_CMD_TBL_ENTRY(                                       \
        "crc32",        3,      4,      1,      do_mem_crc,                     \
        "crc32   - checksum calculation\n",                                     \
-       "address count\n    - compute CRC32 checksum\n"                         \
+       "address count [addr]\n    - compute CRC32 checksum [save at addr]\n"   \
 ),
 #define CMD_TBL_BASE   MK_CMD_TBL_ENTRY(                                       \
        "base",         2,      2,      1,      do_mem_base,                    \

diff --git a/include/config_CPCI405.h b/include/config_CPCI405.h
index c411fa8434a38e6548652770073f22e9c6ff7ba1..85abec482d5c149884fb9141a639844005d35678 100644 (file)
--- a/include/config_CPCI405.h
+++ b/include/config_CPCI405.h
@@ -45,7 +45,11 @@
 #define CONFIG_BOOTDELAY       3       /* autoboot after 3 seconds     */
 
 #if 0
-#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT                                                          \
+        "crc32 f0207004 ffc 0;"                                                 \
+        "if cmp 0 f0207000 1;"                                                  \
+        "then;echo Old CRC is correct;crc32 f0207004 ff4 f0207000;"             \
+        "else;echo Old CRC is bad;fi"
 #endif
 
 #undef CONFIG_BOOTARGS
@@ -100,6 +104,8 @@
 #define CFG_MAXARGS    16              /* max number of command args   */
 #define CFG_BARGSIZE   CFG_CBSIZE      /* Boot Argument Buffer Size    */
 
+#define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
+
 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 
 #define CFG_MEMTEST_START      0x0400000       /* memtest works on     */

diff --git a/include/config_DU405.h b/include/config_DU405.h
index e6e9e590f5ff3f38786f50c7b6c1c0b66d098870..37dc874f74a9ab4b1512448436e34a7d29797e4a 100644 (file)
--- a/include/config_DU405.h
+++ b/include/config_DU405.h
@@ -58,6 +58,7 @@
                                CFG_CMD_IRQ     | \
                                CFG_CMD_IDE     | \
                                CFG_CMD_ELF     | \
+                               CFG_CMD_DATE    | \
                                CFG_CMD_EEPROM  )
 
 #define CONFIG_MAC_PARTITION
@@ -68,6 +69,9 @@
 
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 
+#define CONFIG_RTC_MC146818             /* BQ3285 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR   0xF0000080 /* RTC Base Address         */
+
 /*
  * Miscellaneous configurable options
  */
@@ -127,7 +131,7 @@
  * IDE/ATA stuff
  *-----------------------------------------------------------------------
  */
-#undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
+#undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 #undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
 

diff --git a/include/config_OCRTC.h b/include/config_OCRTC.h
index baad410eb3b2cb350b00975d045096b5c0ebb588..c2335d41cffd37a53e65e66ee7e8bef59c5b11c4 100644 (file)
--- a/include/config_OCRTC.h
+++ b/include/config_OCRTC.h
@@ -119,8 +119,7 @@
 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 
 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0410  /* PCI Device ID: OCRTC         */
 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 #define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
 #define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */

diff --git a/include/config_ORSG.h b/include/config_ORSG.h
new file mode 100644 (file)
index 0000000..c06cc6c
--- /dev/null
+++ b/include/config_ORSG.h
@@ -0,0 +1,239 @@
+/*
+ * (C) Copyright 2001
+ * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_405GP           1       /* This is a PPC405 CPU         */
+#define CONFIG_4xx             1       /* ...member of PPC4xx family   */
+#define CONFIG_ORSG            1       /* ...on a ORSG board           */
+
+#define CONFIG_BOARD_PRE_INIT   1       /* call board_pre_init()        */
+
+#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */
+
+#define CONFIG_BAUDRATE                9600
+#define CONFIG_BOOTDELAY       3       /* autoboot after 3 seconds     */
+
+#undef CONFIG_BOOTARGS
+#define CONFIG_BOOTCOMMAND "go fff00100"
+
+#define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
+#define CFG_LOADS_BAUD_CHANGE  1       /* allow baudrate change        */
+
+#define CONFIG_MII             1       /* MII PHY management           */
+#define        CONFIG_PHY_ADDR         0       /* PHY address                  */
+
+#define CONFIG_COMMANDS              ( CONFIG_CMD_DFL  | \
+                               CFG_CMD_PCI     | \
+                               CFG_CMD_IRQ     | \
+                               CFG_CMD_ASKENV  | \
+                               CFG_CMD_ELF     | \
+                               CFG_CMD_EEPROM  )
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#undef  CONFIG_WATCHDOG                        /* watchdog disabled            */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP                   /* undef to save memory         */
+#define CFG_PROMPT     "=> "           /* Monitor Command Prompt       */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define        CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
+#else
+#define        CFG_CBSIZE      256             /* Console I/O Buffer Size      */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS    16              /* max number of command args   */
+#define CFG_BARGSIZE   CFG_CBSIZE      /* Boot Argument Buffer Size    */
+
+#define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
+
+#define CFG_MEMTEST_START      0x0400000       /* memtest works on     */
+#define CFG_MEMTEST_END                0x0C00000       /* 4 ... 12 MB in DRAM  */
+
+#undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
+#define CFG_BASE_BAUD       691200
+
+/* The following table includes the supported baudrates */
+#define CFG_BAUDRATE_TABLE      \
+        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
+         57600, 115200, 230400, 460800, 921600 }
+
+#define CFG_LOAD_ADDR  0x100000        /* default load address */
+#define CFG_EXTBDINFO  1               /* To use extended board_into (bd_t) */
+
+#define        CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK    /* check for keypress on bootdelay==0 */
+
+/*-----------------------------------------------------------------------
+ * PCI stuff
+ *-----------------------------------------------------------------------
+ */
+#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
+#define PCI_HOST_FORCE  1               /* configure as pci host        */
+#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
+
+#define CONFIG_PCI                     /* include pci support          */
+#define CONFIG_PCI_HOST        PCI_HOST_ADAPTER /* select pci adapter          */
+#undef  CONFIG_PCI_PNP                 /* no pci plug-and-play         */
+                                        /* resource configuration       */
+
+#undef  CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
+
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0411  /* PCI Device ID: ORSG          */
+#define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA  0x00000000      /* point to sdram               */
+#define CFG_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
+#define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
+#define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
+#define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define CFG_SDRAM_BASE         0x00000000
+#define CFG_FLASH_BASE         0xFFFD0000
+#define CFG_MONITOR_BASE       CFG_FLASH_BASE
+#define CFG_MONITOR_LEN                (192 * 1024)    /* Reserve 192 kB for Monitor   */
+#define CFG_MALLOC_LEN         (128 * 1024)    /* Reserve 128 kB for malloc()  */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ          (8 << 20)       /* Initial Memory map for Linux */
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS    2       /* max number of memory banks           */
+#define CFG_MAX_FLASH_SECT     256     /* max number of sectors on one chip    */
+
+#define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)      */
+#define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms)      */
+
+#define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
+#define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
+#define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
+/*
+ * The following defines are added for buggy IOP480 byte interface.
+ * All other boards should use the standard values (CPCI405 etc.)
+ */
+#define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
+#define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
+#define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
+
+#define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
+
+#if 0 /* Use NVRAM for environment variables */
+/*-----------------------------------------------------------------------
+ * NVRAM organization
+ */
+#define CFG_ENV_IS_IN_NVRAM    1       /* use NVRAM for environment vars       */
+#define CFG_NVRAM_BASE_ADDR    0xf0200000              /* NVRAM base address   */
+#define CFG_NVRAM_SIZE         (32*1024)               /* NVRAM size           */
+#define CFG_ENV_SIZE           0x1000          /* Size of Environment vars     */
+#define CFG_ENV_ADDR           \
+       (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)       /* Env  */
+#define CFG_NVRAM_VXWORKS_OFFS 0x6900          /* Offset for VxWorks eth-addr  */
+
+#else /* Use EEPROM for environment variables */
+/*-----------------------------------------------------------------------
+ * I2C EEPROM (CAT24WC08) for environment
+ */
+#undef  CONFIG_I2C_X                    /* 8 bit access */
+#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET          0x000   /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE            0x300   /* 768 bytes may be used for env vars */
+                                   /* total size of a CAT24WC08 is 1024 bytes */
+#endif
+
+#define CFG_I2C_EEPROM_ADDR    0x50    /* EEPROM CAT28WC08             */
+#define CFG_EEPROM_PAGE_WRITE_BITS 4   /* The Catalyst CAT24WC08 has   */
+                                       /* 16 byte page write mode using*/
+                                       /* last 4 bits of the address   */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE     16      /* For all MPC8xx CPUs                  */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT    4       /* log base 2 of the above value        */
+#endif
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM     0xFF800000      /* FLASH bank #0        */
+#define FLASH_BASE1_PRELIM     0xFFC00000      /* FLASH bank #1        */
+
+
+/* On Chip Memory location */
+#define OCM_DATA_ADDR          0xF8000000
+
+#define CFG_ETHERNET_MAC_ADDR   0x00000000      /* Pass Ethernet MAC to VxWorks */
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR      0x00df0000 /* inside of SDRAM                   */
+#define CFG_INIT_RAM_END       0x0f00  /* End of used area in RAM             */
+#define CFG_INIT_DATA_SIZE     64  /* size in bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET     CFG_INIT_DATA_OFFSET
+
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD  0x01            /* Normal Power-On: Boot from FLASH     */
+#define BOOTFLAG_WARM  0x02            /* Software reboot                      */
+
+#endif /* __CONFIG_H */

diff --git a/include/config_ZUMA.h b/include/config_ZUMA.h
index 8cd6cf2f56531a0cc7afac097f995e356043af56..c39c12abf2971b6abcb6232f5882eef788e62dcd 100644 (file)
--- a/include/config_ZUMA.h
+++ b/include/config_ZUMA.h
@@ -185,12 +185,12 @@
 #define CFG_DEV2_SIZE           _8M /* unused */
 #define CFG_DEV3_SIZE           _8M /* unused */
 
-#define CFG_DEV0_PAR           0xc498241c
-       /*   c    4    9      8     2     4    1      c */
-       /* 33 22|2222|22 22|111 1|11 11|1 1  |    | */
+#define CFG_DEV0_PAR           0xc498243c
+       /*     c    4     9     8     2     4     3     c */
+       /* 33 22|2222|22 22|111 1|11 11|1 1  |     |      */
        /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
-       /* 11|00|0100|10 01|100|0 00|10 0|100 0|001 1|100 */
-       /*  3| 0|.... ..| 1| 4 |  0 |  4 |  8  |  3  | 4 */
+       /* 11|00|0100|10 01|100|0 00|10 0|100 0|011 1|100 */
+       /*  3| 0|.... ..| 1| 4 |  0 |  4 |   8 |   7 | 4  */
 
 #define CFG_8BIT_BOOT_PAR      0xc00b5e7c
 

diff --git a/include/flash.h b/include/flash.h
index b2802116818c88c3f529ab8dbbeacccc9547c5f7..153dd81c5646fd3005885ab0fb9650acb99a8dd3 100644 (file)
--- a/include/flash.h
+++ b/include/flash.h
@@ -130,9 +130,8 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot);
 #define AMD_ID_LV160T  0x22C422C4      /* 29LV160T ID (16 M, top boot sector)  */
 #define AMD_ID_LV160B  0x22492249      /* 29LV160B ID (16 M, bottom boot sect) */
 
-/* 29LV320 device IDs are not yet available */
-#define AMD_ID_LV320T  0xDEADBEEF      /* 29LV320T ID (32 M, top boot sector)  */
-#define AMD_ID_LV320B  0xDEADBEEF      /* 29LV320B ID (32 M, bottom boot sect) */
+#define AMD_ID_LV320T  0x22F622F6      /* 29LV320T ID (32 M, top boot sector)  */
+#define AMD_ID_LV320B  0x22F922F9      /* 29LV320B ID (32 M, bottom boot sect) */
 
 #define AMD_ID_DL322T  0x22552255      /* 29DL322T ID (32 M, top boot sector)  */
 #define AMD_ID_DL322B  0x22562256      /* 29DL322B ID (32 M, bottom boot sect) */

diff --git a/include/mpc8260.h b/include/mpc8260.h
index 1e68426ad0de87bf57bc171f42d7470f1575a68f..296a585f31ba158b30171cf9de4ab2a2c11a7bc9 100644 (file)
--- a/include/mpc8260.h
+++ b/include/mpc8260.h
@@ -138,7 +138,7 @@
 #define SIUMCR_L2CPC11 0x03000000      /* - " -                        */
 #define SIUMCR_LBPC00  0x00000000      /* Local Bus Pins Configuration */
 #define SIUMCR_LBPC01  0x00400000      /* - " -                        */
-#define SIUMCR_LBP010  0x00800000      /* - " -                        */
+#define SIUMCR_LBPC10  0x00800000      /* - " -                        */
 #define SIUMCR_LBPC11  0x00c00000      /* - " -                        */
 #define SIUMCR_APPC00  0x00000000      /* Address Parity Pins Configuration*/
 #define SIUMCR_APPC01  0x00100000      /* - " -                        */

diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index b10283c95a384a1ff391dfa148a65b031ff866a7..f88d4249b1d10ac7ba2d665208beeeef17d8c418 100644 (file)
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -366,6 +366,7 @@
  * Macro for accessing the indirect EBC register
  */
 #define mtebc(reg, data)  mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
+#define mfebc(reg, data)  mtdcr(ebccfga,reg);data = mfdcr(ebccfgd)
 
 
 #ifndef __ASSEMBLY__

diff --git a/include/ppcboot.h b/include/ppcboot.h
index dffbee90dbf94516a42d7cbda264fc8dceba68c3..6cc51cae4be3b2ab05527c083f02cad74e834cae 100644 (file)
--- a/include/ppcboot.h
+++ b/include/ppcboot.h
@@ -190,19 +190,14 @@ int       saveenv(void);
 void inline  setenv (char *, char *);
 
 #if defined(CONFIG_PCI)                || \
-    defined(CONFIG_AR405)      || \
     defined(CONFIG_BAB750)     || \
-    defined(CONFIG_CPCI405)    || \
-    defined(CONFIG_CPCIISER4)  || \
     defined(CONFIG_DASA_SIM)   || \
     defined(CONFIG_EVB64260)   || \
-    defined(CONFIG_DU405)      || \
     defined(CONFIG_ERIC)       || \
     defined(CONFIG_EVB64260)   || \
     defined(CONFIG_MIP405)     || \
     defined(CONFIG_MOUSSE)     || \
     defined(CONFIG_MUSENKI)    || \
-    defined(CONFIG_OCRTC)      || \
     defined(CONFIG_PIP405)     || \
     defined(CONFIG_SANDPOINT)  || \
     defined(CONFIG_W7O)                || \
@@ -248,6 +243,7 @@ void        reset_phy     (void);
     defined(CONFIG_IP860)      || \
     defined(CONFIG_LWMON)      || \
     defined(CONFIG_OCRTC)      || \
+    defined(CONFIG_ORSG)       || \
     defined(CONFIG_PCU_E)      || \
     defined(CONFIG_PIP405)     || \
     defined(CONFIG_MIP405)     || \
@@ -314,18 +310,11 @@ void  perform_soft_reset(void);
 void   load_sernum_ethaddr(bd_t *bd);
 #endif
 
-#if defined(CONFIG_ADCIOP)     || \
-    defined(CONFIG_AR405)      || \
-    defined(CONFIG_CANBT)      || \
-    defined(CONFIG_CPCI405)    || \
-    defined(CONFIG_CPCIISER4)  || \
-    defined(CONFIG_CU824)      || \
-    defined(CONFIG_DASA_SIM)   || \
+#if defined(CONFIG_CU824)      || \
     defined(CONFIG_EP8260)     || \
     defined(CONFIG_LWMON)      || \
     defined(CONFIG_MIP405)     || \
     defined(CONFIG_MPC8260ADS) || \
-    defined(CONFIG_OCRTC)      || \
     defined(CONFIG_PIP405)     || \
     defined(CONFIG_RPXSUPER)   || \
     defined(CONFIG_W7O)                || \

diff --git a/rtc/mc146818.c b/rtc/mc146818.c
index 6469391405bcb04fb6a76ce8d92583f223940320..3731115630d553f6679a152d4bf161db66e941a2 100644 (file)
--- a/rtc/mc146818.c
+++ b/rtc/mc146818.c
@@ -132,6 +132,20 @@ void rtc_reset (void)
 
 /* ------------------------------------------------------------------------- */
 
+#ifdef CFG_RTC_REG_BASE_ADDR
+/*
+ * use direct memory access
+ */
+static uchar rtc_read (uchar reg)
+{
+       return(in8(CFG_RTC_REG_BASE_ADDR+reg));
+}
+
+static void rtc_write (uchar reg, uchar val)
+{
+       out8(CFG_RTC_REG_BASE_ADDR+reg, val);
+}
+#else
 static uchar rtc_read (uchar reg)
 {
        out8(RTC_PORT_MC146818,reg);
@@ -143,6 +157,7 @@ static void rtc_write (uchar reg, uchar val)
        out8(RTC_PORT_MC146818,reg);
        out8(RTC_PORT_MC146818+1,val);
 }
+#endif
 
 static unsigned bcd2bin (uchar n)
 {