arm64: dts: mediatek: mt8195: Assign USB 3.0 PHY to xhci1 by default

xhci1 has both USB 2.0 and USB 3.0 host capabilities. By default both
are assumed to be enabled when the controller is enabled. To disable
either one, an extra property is used.

Since the default has both enabled, both PHYs should also be assigned
to the host controller. If a specific design uses only either one,
the board specific dts file can override the PHY assignment together
with adding the "mediatek,u[23]p-dis-msk" property. This keeps both
changes together.

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20240731034411.371178-4-wenst@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
index d535fa6dc9d3833d23438c26e5c4db5ce1ff33f0..75d56b2d5a3d346734012062db8cb0ac885b88da 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
@@ -1397,6 +1397,7 @@
 &xhci1 {
        status = "okay";
 
+       phys = <&u2port1 PHY_TYPE_USB2>;
        rx-fifo-depth = <3072>;
        vusb33-supply = <&mt6359_vusb_ldo_reg>;
        vbus-supply = <&usb_vbus>;

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index a46062258603a825228be431dc8b4829a9920063..989e8ac545ac109a063ccaa5e8f470f00d086125 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1444,7 +1444,7 @@
                              <0 0x11293e00 0 0x0100>;
                        reg-names = "mac", "ippc";
                        interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
-                       phys = <&u2port1 PHY_TYPE_USB2>;
+                       phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
                        assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
                                          <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
                        assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,

diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
index a06610fff8adef57c2b5c0e0db3bab95e05ca5d6..1ef6262b65c9ac0cfc2f9dd3c7dc25daf673010d 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
@@ -904,8 +904,6 @@
 };
 
 &xhci1 {
-       phys = <&u2port1 PHY_TYPE_USB2>,
-              <&u3port1 PHY_TYPE_USB3>;
        vusb33-supply = <&mt6359_vusb_ldo_reg>;
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts b/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts
index e4b2af9489a8931fa75ca821511e931f02303ea3..e2e75b8ff91880711c82f783c7ccbef4128b7ab4 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts
@@ -1111,6 +1111,7 @@
 
 /* USB2.0 M.2 Key-B */
 &xhci1 {
+       phys = <&u2port1 PHY_TYPE_USB2>;
        vusb33-supply = <&mt6359_vusb_ldo_reg>;
        mediatek,u3p-dis-msk = <0x01>;
        status = "okay";

diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
index 096fa999aa59ecae8dbaf1ecbf8fa3dd172545df..14ec970c4e491fbd69bf2800639abf726d47589a 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
@@ -894,6 +894,7 @@
 };
 
 &xhci1 {
+       phys = <&u2port1 PHY_TYPE_USB2>;
        /* MT7921's USB Bluetooth has issues with USB2 LPM */
        usb2-lpm-disable;
        vusb33-supply = <&mt6359_vusb_ldo_reg>;