arm64/sysreg: Add register fields for ID_AA64DFR1_EL1

This adds register fields for ID_AA64DFR1_EL1 as per the definitions based
on DDI0601 2023-12.

Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20240220023203.3091229-1-anshuman.khandual@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 4c9b679343674ab0ceaa04799654757391dd262c..dd693f992832c9897bf5647ecc68c4123b2e4472 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1251,7 +1251,36 @@ EndEnum
 EndSysreg
 
 Sysreg ID_AA64DFR1_EL1 3       0       0       5       1
-Res0   63:0
+Field  63:56   ABL_CMPs
+UnsignedEnum   55:52   DPFZS
+       0b0000  IGNR
+       0b0001  FRZN
+EndEnum
+UnsignedEnum   51:48   EBEP
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+UnsignedEnum   47:44   ITE
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+UnsignedEnum   43:40   ABLE
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+UnsignedEnum   39:36   PMICNTR
+       0b0000  NI
+       0b0001  IMP
+EndEnum
+UnsignedEnum   35:32   SPMU
+       0b0000  NI
+       0b0001  IMP
+       0b0010  IMP_SPMZR
+EndEnum
+Field  31:24   CTX_CMPs
+Field  23:16   WRPs
+Field  15:8    BRPs
+Field  7:0     SYSPMUID
 EndSysreg
 
 Sysreg ID_AA64AFR0_EL1 3       0       0       5       4