drm/amd/display: Check null pointers before multiple uses

[WHAT & HOW]
Poniters, such as stream_enc and dc->bw_vbios, are null checked previously
in the same function, so Coverity warns "implies that stream_enc and
dc->bw_vbios might be null". They are used multiple times in the
subsequent code and need to be checked.

This fixes 10 FORWARD_NULL issues reported by Coverity.

Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 9e42a0128baa397f3bdf09c18c58f3b9c2f7d0da..5f9b6e8ef428cdde4a35762e3adbc70fb3a8c8cf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -636,57 +636,59 @@ void hwss_build_fast_sequence(struct dc *dc,
        while (current_pipe) {
                current_mpc_pipe = current_pipe;
                while (current_mpc_pipe) {
-                       if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state && current_mpc_pipe->plane_state->update_flags.raw) {
-                               block_sequence[*num_steps].params.set_flip_control_gsl_params.pipe_ctx = current_mpc_pipe;
-                               block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe->plane_state->flip_immediate;
-                               block_sequence[*num_steps].func = HUBP_SET_FLIP_CONTROL_GSL;
-                               (*num_steps)++;
-                       }
-                       if (dc->hwss.program_triplebuffer && dc->debug.enable_tri_buf && current_mpc_pipe->plane_state->update_flags.raw) {
-                               block_sequence[*num_steps].params.program_triplebuffer_params.dc = dc;
-                               block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe;
-                               block_sequence[*num_steps].params.program_triplebuffer_params.enableTripleBuffer = current_mpc_pipe->plane_state->triplebuffer_flips;
-                               block_sequence[*num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER;
-                               (*num_steps)++;
-                       }
-                       if (dc->hwss.update_plane_addr && current_mpc_pipe->plane_state->update_flags.bits.addr_update) {
-                               if (resource_is_pipe_type(current_mpc_pipe, OTG_MASTER) &&
-                                               stream_status->mall_stream_config.type == SUBVP_MAIN) {
-                                       block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;
-                                       block_sequence[*num_steps].params.subvp_save_surf_addr.addr = &current_mpc_pipe->plane_state->address;
-                                       block_sequence[*num_steps].params.subvp_save_surf_addr.subvp_index = current_mpc_pipe->subvp_index;
-                                       block_sequence[*num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR;
+                       if (current_mpc_pipe->plane_state) {
+                               if (dc->hwss.set_flip_control_gsl && current_mpc_pipe->plane_state->update_flags.raw) {
+                                       block_sequence[*num_steps].params.set_flip_control_gsl_params.pipe_ctx = current_mpc_pipe;
+                                       block_sequence[*num_steps].params.set_flip_control_gsl_params.flip_immediate = current_mpc_pipe->plane_state->flip_immediate;
+                                       block_sequence[*num_steps].func = HUBP_SET_FLIP_CONTROL_GSL;
+                                       (*num_steps)++;
+                               }
+                               if (dc->hwss.program_triplebuffer && dc->debug.enable_tri_buf && current_mpc_pipe->plane_state->update_flags.raw) {
+                                       block_sequence[*num_steps].params.program_triplebuffer_params.dc = dc;
+                                       block_sequence[*num_steps].params.program_triplebuffer_params.pipe_ctx = current_mpc_pipe;
+                                       block_sequence[*num_steps].params.program_triplebuffer_params.enableTripleBuffer = current_mpc_pipe->plane_state->triplebuffer_flips;
+                                       block_sequence[*num_steps].func = HUBP_PROGRAM_TRIPLEBUFFER;
+                                       (*num_steps)++;
+                               }
+                               if (dc->hwss.update_plane_addr && current_mpc_pipe->plane_state->update_flags.bits.addr_update) {
+                                       if (resource_is_pipe_type(current_mpc_pipe, OTG_MASTER) &&
+                                                       stream_status->mall_stream_config.type == SUBVP_MAIN) {
+                                               block_sequence[*num_steps].params.subvp_save_surf_addr.dc_dmub_srv = dc->ctx->dmub_srv;
+                                               block_sequence[*num_steps].params.subvp_save_surf_addr.addr = &current_mpc_pipe->plane_state->address;
+                                               block_sequence[*num_steps].params.subvp_save_surf_addr.subvp_index = current_mpc_pipe->subvp_index;
+                                               block_sequence[*num_steps].func = DMUB_SUBVP_SAVE_SURF_ADDR;
+                                               (*num_steps)++;
+                                       }
+
+                                       block_sequence[*num_steps].params.update_plane_addr_params.dc = dc;
+                                       block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe;
+                                       block_sequence[*num_steps].func = HUBP_UPDATE_PLANE_ADDR;
                                        (*num_steps)++;
                                }
 
-                               block_sequence[*num_steps].params.update_plane_addr_params.dc = dc;
-                               block_sequence[*num_steps].params.update_plane_addr_params.pipe_ctx = current_mpc_pipe;
-                               block_sequence[*num_steps].func = HUBP_UPDATE_PLANE_ADDR;
-                               (*num_steps)++;
-                       }
-
-                       if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) {
-                               block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc;
-                               block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;
-                               block_sequence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe->plane_state;
-                               block_sequence[*num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC;
-                               (*num_steps)++;
-                       }
+                               if (hws->funcs.set_input_transfer_func && current_mpc_pipe->plane_state->update_flags.bits.gamma_change) {
+                                       block_sequence[*num_steps].params.set_input_transfer_func_params.dc = dc;
+                                       block_sequence[*num_steps].params.set_input_transfer_func_params.pipe_ctx = current_mpc_pipe;
+                                       block_sequence[*num_steps].params.set_input_transfer_func_params.plane_state = current_mpc_pipe->plane_state;
+                                       block_sequence[*num_steps].func = DPP_SET_INPUT_TRANSFER_FUNC;
+                                       (*num_steps)++;
+                               }
 
-                       if (dc->hwss.program_gamut_remap && current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change) {
-                               block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe;
-                               block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP;
-                               (*num_steps)++;
-                       }
-                       if (current_mpc_pipe->plane_state->update_flags.bits.input_csc_change) {
-                               block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe;
-                               block_sequence[*num_steps].func = DPP_SETUP_DPP;
-                               (*num_steps)++;
-                       }
-                       if (current_mpc_pipe->plane_state->update_flags.bits.coeff_reduction_change) {
-                               block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe;
-                               block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;
-                               (*num_steps)++;
+                               if (dc->hwss.program_gamut_remap && current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change) {
+                                       block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe;
+                                       block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP;
+                                       (*num_steps)++;
+                               }
+                               if (current_mpc_pipe->plane_state->update_flags.bits.input_csc_change) {
+                                       block_sequence[*num_steps].params.setup_dpp_params.pipe_ctx = current_mpc_pipe;
+                                       block_sequence[*num_steps].func = DPP_SETUP_DPP;
+                                       (*num_steps)++;
+                               }
+                               if (current_mpc_pipe->plane_state->update_flags.bits.coeff_reduction_change) {
+                                       block_sequence[*num_steps].params.program_bias_and_scale_params.pipe_ctx = current_mpc_pipe;
+                                       block_sequence[*num_steps].func = DPP_PROGRAM_BIAS_AND_SCALE;
+                                       (*num_steps)++;
+                               }
                        }
                        if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) {
                                block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index dd652436a5392022767e8989f7c697807fd32f51..bd7b186fb2e4699859cf7374a1c3db99fffe3b35 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -2284,6 +2284,9 @@ void dcn20_post_unlock_program_front_end(
                }
        }
 
+       if (!hwseq)
+               return;
+
        /* P-State support transitions:
         * Natural -> FPO:              P-State disabled in prepare, force disallow anytime is safe
         * FPO -> Natural:              Unforce anytime after FW disable is safe (P-State will assert naturally)
@@ -2291,7 +2294,7 @@ void dcn20_post_unlock_program_front_end(
         * FPO -> Unsupported:  P-State disabled in prepare, unforce disallow anytime is safe
         * FPO <-> SubVP:               Force disallow is maintained on the FPO / SubVP pipes
         */
-       if (hwseq && hwseq->funcs.update_force_pstate)
+       if (hwseq->funcs.update_force_pstate)
                dc->hwseq->funcs.update_force_pstate(dc, context);
 
        /* Only program the MALL registers after all the main and phantom pipes
@@ -2531,6 +2534,9 @@ bool dcn20_wait_for_blank_complete(
 {
        int counter;
 
+       if (!opp)
+               return false;
+
        for (counter = 0; counter < 1000; counter++) {
                if (!opp->funcs->dpg_is_pending(opp))
                        break;

diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
index 555c1c484cfddcbe1d91e806d88a846ae5e3fc9d..df3781081da7aeb97d9b8c927cee6b3d398fe20e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
+++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
@@ -804,8 +804,11 @@ bool dp_set_test_pattern(
                        break;
                }
 
+               if (!pipe_ctx->stream)
+                       return false;
+
                if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) {
-                       if (pipe_ctx->stream && should_use_dmub_lock(pipe_ctx->stream->link)) {
+                       if (should_use_dmub_lock(pipe_ctx->stream->link)) {
                                union dmub_hw_lock_flags hw_locks = { 0 };
                                struct dmub_hw_lock_inst_flags inst_flags = { 0 };
 

diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
index b76737b7b9e41bc36ce5bb6591cd5b936c1d2d37..3e47a6735912a576f9f07dc2137764d7eca441cd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dio.c
@@ -74,7 +74,10 @@ void reset_dio_stream_encoder(struct pipe_ctx *pipe_ctx)
        struct link_encoder *link_enc = link_enc_cfg_get_link_enc(pipe_ctx->stream->link);
        struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc;
 
-       if (stream_enc && stream_enc->funcs->disable_fifo)
+       if (!stream_enc)
+               return;
+
+       if (stream_enc->funcs->disable_fifo)
                stream_enc->funcs->disable_fifo(stream_enc);
        if (stream_enc->funcs->set_input_mode)
                stream_enc->funcs->set_input_mode(stream_enc, 0);

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
index 88afb2a30eef500cdba1481cb0e1f7be732ca7ed..162856c523e40c3c9c8849f5bbec2e49944b4593 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce112/dce112_resource.c
@@ -1067,7 +1067,10 @@ static void bw_calcs_data_update_from_pplib(struct dc *dc)
        struct dm_pp_clock_levels clks = {0};
        int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
 
-       if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm)
+       if (!dc->bw_vbios)
+               return;
+
+       if (dc->bw_vbios->memory_type == bw_def_hbm)
                memory_type_multiplier = MEMORY_TYPE_HBM;
 
        /*do system clock  TODO PPLIB: after PPLIB implement,

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
index ee009716d39b1fe170c4ef73a9bd2643ca60cd9b..6eaf3cfebcb7f75384045c96d638830a0618ca68 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
@@ -1651,6 +1651,9 @@ static void dcn32_enable_phantom_plane(struct dc *dc,
                else
                        phantom_plane = dc_state_create_phantom_plane(dc, context, curr_pipe->plane_state);
 
+               if (!phantom_plane)
+                       continue;
+
                memcpy(&phantom_plane->address, &curr_pipe->plane_state->address, sizeof(phantom_plane->address));
                memcpy(&phantom_plane->scaling_quality, &curr_pipe->plane_state->scaling_quality,
                                sizeof(phantom_plane->scaling_quality));

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
index d184105ce2b3e6628c68ba2f168d686375bb952a..47c8a9fbe75467d4328ec2327f78079dbb48d72d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
@@ -218,12 +218,12 @@ bool dcn32_is_center_timing(struct pipe_ctx *pipe)
                                pipe->stream->timing.v_addressable != pipe->stream->src.height) {
                        is_center_timing = true;
                }
-       }
 
-       if (pipe->plane_state) {
-               if (pipe->stream->timing.v_addressable != pipe->plane_state->dst_rect.height &&
-                               pipe->stream->timing.v_addressable != pipe->plane_state->src_rect.height) {
-                       is_center_timing = true;
+               if (pipe->plane_state) {
+                       if (pipe->stream->timing.v_addressable != pipe->plane_state->dst_rect.height &&
+                                       pipe->stream->timing.v_addressable != pipe->plane_state->src_rect.height) {
+                               is_center_timing = true;
+                       }
                }
        }