guc->notify = gen8_guc_raise_irq;
 }
 
-static u32 get_gttype(struct drm_i915_private *dev_priv)
+static u32 get_gt_type(struct drm_i915_private *dev_priv)
 {
        /* XXX: GT type based on PCI device ID? field seems unused by fw */
        return 0;
        u32 params[GUC_CTL_MAX_DWORDS];
        int i;
 
-       memset(¶ms, 0, sizeof(params));
+       memset(params, 0, sizeof(params));
 
        params[GUC_CTL_DEVICE_INFO] |=
-               (get_gttype(dev_priv) << GUC_CTL_GTTYPE_SHIFT) |
-               (get_core_family(dev_priv) << GUC_CTL_COREFAMILY_SHIFT);
+               (get_gt_type(dev_priv) << GUC_CTL_GT_TYPE_SHIFT) |
+               (get_core_family(dev_priv) << GUC_CTL_CORE_FAMILY_SHIFT);
 
        /*
         * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
        if (i915_modparams.guc_log_level >= 0) {
                params[GUC_CTL_DEBUG] =
                        i915_modparams.guc_log_level << GUC_LOG_VERBOSITY_SHIFT;
-       } else
+       } else {
                params[GUC_CTL_DEBUG] = GUC_LOG_DISABLED;
+       }
 
        /* If GuC submission is enabled, set up additional parameters here */
        if (i915_modparams.enable_guc_submission) {
 
 #define GUC_CTL_ARAT_LOW               2
 
 #define GUC_CTL_DEVICE_INFO            3
-#define   GUC_CTL_GTTYPE_SHIFT         0
-#define   GUC_CTL_COREFAMILY_SHIFT     7
+#define   GUC_CTL_GT_TYPE_SHIFT                0
+#define   GUC_CTL_CORE_FAMILY_SHIFT    7
 
 #define GUC_CTL_LOG_PARAMS             4
 #define   GUC_LOG_VALID                        (1 << 0)