ARM: dts: qcom: sdx65-mtp: Enable PCIe EP

Enable PCIe Endpoint controller on the SDX65 MTP board based
on Qualcomm SDX65 platform.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1684432073-28490-6-git-send-email-quic_rohiagar@quicinc.com

diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
index 29ccb158f8fc4ca194d1d885e8e560677f993ba1..02d8d6e241ae16477f50984853f4d5253b9e4e36 100644 (file)
--- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts
+++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts
@@ -250,6 +250,18 @@
        status = "okay";
 };
 
+&pcie_ep {
+       pinctrl-0 = <&pcie_ep_clkreq_default
+                    &pcie_ep_perst_default
+                    &pcie_ep_wake_default>;
+       pinctrl-names = "default";
+
+       reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+       wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
+
+       status = "okay";
+};
+
 &pcie_phy {
        vdda-phy-supply = <&vreg_l1b_1p2>;
        vdda-pll-supply = <&vreg_l4b_0p88>;
@@ -281,6 +293,29 @@
        status = "okay";
 };
 
+&tlmm {
+       pcie_ep_clkreq_default: pcie-ep-clkreq-default-state {
+               pins = "gpio56";
+               function = "pcie_clkreq";
+               drive-strength = <2>;
+               bias-disable;
+       };
+
+       pcie_ep_perst_default: pcie-ep-perst-default-state {
+               pins = "gpio57";
+               function = "gpio";
+               drive-strength = <2>;
+               bias-pull-down;
+       };
+
+       pcie_ep_wake_default: pcie-ep-wake-default-state {
+               pins = "gpio53";
+               function = "gpio";
+               drive-strength = <2>;
+               bias-disable;
+       };
+};
+
 &usb {
        status = "okay";
 };