void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo);
 
+int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
+                               struct tile_config *config);
+
 /* KGD2KFD callbacks */
 int kgd2kfd_init(void);
 void kgd2kfd_exit(void);
 
        .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
        .get_atc_vmid_pasid_mapping_info =
                        kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
-       .get_tile_config = kgd_gfx_v9_get_tile_config,
        .set_vm_context_page_table_base = kgd_set_vm_context_page_table_base,
        .get_hive_id = amdgpu_amdkfd_get_hive_id,
 };
 
        SAVE_WAVES
 };
 
-/* Because of REG_GET_FIELD() being used, we put this function in the
- * asic specific file.
- */
-static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
-               struct tile_config *config)
-{
-       struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
-
-       config->gb_addr_config = adev->gfx.config.gb_addr_config;
-#if 0
-/* TODO - confirm REG_GET_FIELD x2, should be OK as is... but
- * MC_ARB_RAMCFG register doesn't exist on Vega10 - initial amdgpu
- * changes commented out related code, doing the same here for now but
- * need to sync with Ken et al
- */
-       config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
-                               MC_ARB_RAMCFG, NOOFBANK);
-       config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
-                               MC_ARB_RAMCFG, NOOFRANKS);
-#endif
-
-       config->tile_config_ptr = adev->gfx.config.tile_mode_array;
-       config->num_tile_configs =
-                       ARRAY_SIZE(adev->gfx.config.tile_mode_array);
-       config->macro_tile_config_ptr =
-                       adev->gfx.config.macrotile_mode_array;
-       config->num_macro_tile_configs =
-                       ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
-
-       return 0;
-}
-
 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 {
        return (struct amdgpu_device *)kgd;
        .address_watch_get_offset = kgd_address_watch_get_offset,
        .get_atc_vmid_pasid_mapping_info =
                        get_atc_vmid_pasid_mapping_info,
-       .get_tile_config = amdgpu_amdkfd_get_tile_config,
        .set_vm_context_page_table_base = set_vm_context_page_table_base,
        .get_hive_id = amdgpu_amdkfd_get_hive_id,
        .get_unique_id = amdgpu_amdkfd_get_unique_id,
 
        float f32All;
 };
 
-/* Because of REG_GET_FIELD() being used, we put this function in the
- * asic specific file.
- */
-static int get_tile_config(struct kgd_dev *kgd,
-               struct tile_config *config)
-{
-       struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
-
-       config->gb_addr_config = adev->gfx.config.gb_addr_config;
-       config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
-                               MC_ARB_RAMCFG, NOOFBANK);
-       config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
-                               MC_ARB_RAMCFG, NOOFRANKS);
-
-       config->tile_config_ptr = adev->gfx.config.tile_mode_array;
-       config->num_tile_configs =
-                       ARRAY_SIZE(adev->gfx.config.tile_mode_array);
-       config->macro_tile_config_ptr =
-                       adev->gfx.config.macrotile_mode_array;
-       config->num_macro_tile_configs =
-                       ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
-
-       return 0;
-}
-
 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 {
        return (struct amdgpu_device *)kgd;
        .address_watch_get_offset = kgd_address_watch_get_offset,
        .get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info,
        .set_scratch_backing_va = set_scratch_backing_va,
-       .get_tile_config = get_tile_config,
        .set_vm_context_page_table_base = set_vm_context_page_table_base,
        .read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg,
 };
 
        RESET_WAVES
 };
 
-/* Because of REG_GET_FIELD() being used, we put this function in the
- * asic specific file.
- */
-static int get_tile_config(struct kgd_dev *kgd,
-               struct tile_config *config)
-{
-       struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
-
-       config->gb_addr_config = adev->gfx.config.gb_addr_config;
-       config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
-                               MC_ARB_RAMCFG, NOOFBANK);
-       config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg,
-                               MC_ARB_RAMCFG, NOOFRANKS);
-
-       config->tile_config_ptr = adev->gfx.config.tile_mode_array;
-       config->num_tile_configs =
-                       ARRAY_SIZE(adev->gfx.config.tile_mode_array);
-       config->macro_tile_config_ptr =
-                       adev->gfx.config.macrotile_mode_array;
-       config->num_macro_tile_configs =
-                       ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
-
-       return 0;
-}
-
 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 {
        return (struct amdgpu_device *)kgd;
        .get_atc_vmid_pasid_mapping_info =
                        get_atc_vmid_pasid_mapping_info,
        .set_scratch_backing_va = set_scratch_backing_va,
-       .get_tile_config = get_tile_config,
        .set_vm_context_page_table_base = set_vm_context_page_table_base,
 };
 
        RESET_WAVES
 };
 
-
-/* Because of REG_GET_FIELD() being used, we put this function in the
- * asic specific file.
- */
-int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd,
-               struct tile_config *config)
-{
-       struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
-
-       config->gb_addr_config = adev->gfx.config.gb_addr_config;
-
-       config->tile_config_ptr = adev->gfx.config.tile_mode_array;
-       config->num_tile_configs =
-                       ARRAY_SIZE(adev->gfx.config.tile_mode_array);
-       config->macro_tile_config_ptr =
-                       adev->gfx.config.macrotile_mode_array;
-       config->num_macro_tile_configs =
-                       ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
-
-       return 0;
-}
-
 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
 {
        return (struct amdgpu_device *)kgd;
        .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset,
        .get_atc_vmid_pasid_mapping_info =
                        kgd_gfx_v9_get_atc_vmid_pasid_mapping_info,
-       .get_tile_config = kgd_gfx_v9_get_tile_config,
        .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base,
        .get_hive_id = amdgpu_amdkfd_get_hive_id,
        .get_unique_id = amdgpu_amdkfd_get_unique_id,
 
 
 bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd,
                                        uint8_t vmid, uint16_t *p_pasid);
-int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd,
-               struct tile_config *config);
 
        kfree(mem);
        return 0;
 }
+
+/* Returns GPU-specific tiling mode information */
+int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
+                               struct tile_config *config)
+{
+       struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
+
+       config->gb_addr_config = adev->gfx.config.gb_addr_config;
+       config->tile_config_ptr = adev->gfx.config.tile_mode_array;
+       config->num_tile_configs =
+                       ARRAY_SIZE(adev->gfx.config.tile_mode_array);
+       config->macro_tile_config_ptr =
+                       adev->gfx.config.macrotile_mode_array;
+       config->num_macro_tile_configs =
+                       ARRAY_SIZE(adev->gfx.config.macrotile_mode_array);
+
+       /* Those values are not set from GFX9 onwards */
+       config->num_banks = adev->gfx.config.num_banks;
+       config->num_ranks = adev->gfx.config.num_ranks;
+
+       return 0;
+}
 
        if (!dev)
                return -EINVAL;
 
-       dev->kfd2kgd->get_tile_config(dev->kgd, &config);
+       amdgpu_amdkfd_get_tile_config(dev->kgd, &config);
 
        args->gb_addr_config = config.gb_addr_config;
        args->num_banks = config.num_banks;
 
  * @set_scratch_backing_va: Sets VA for scratch backing memory of a VMID.
  * Only used for no cp scheduling mode
  *
- * @get_tile_config: Returns GPU-specific tiling mode information
- *
  * @set_vm_context_page_table_base: Program page table base for a VMID
  *
  * @invalidate_tlbs: Invalidate TLBs for a specific PASID
        void (*set_scratch_backing_va)(struct kgd_dev *kgd,
                                uint64_t va, uint32_t vmid);
 
-       int (*get_tile_config)(struct kgd_dev *kgd, struct tile_config *config);
-
        void (*set_vm_context_page_table_base)(struct kgd_dev *kgd,
                        uint32_t vmid, uint64_t page_table_base);
        uint32_t (*read_vmid_from_vmfault_reg)(struct kgd_dev *kgd);