Modifications since 0.6.0:
======================================================================
+* MBX8xx support (thanks to Marius Gröger)
+
* Fix violation of BOOTP message format.
* Allow for configurations which don't define some environment
FADS823 FADS850SAR FADS860T \
CPCI405 ADCIOP \
cogent_mpc8xx \
- GENIETV
-
+ GENIETV \
+ MBX
do
make distclean >/dev/null
make ${i}_config
}
s = getenv ("ethaddr");
+
+#ifdef CONFIG_MBX
+ if (s == NULL)
+ board_get_enetaddr(bd->bi_enetaddr);
+ else
+#endif
for (reg=0; reg<6; ++reg) {
bd->bi_enetaddr[reg] = s ? simple_strtoul(s, &e, 16) : 0;
if (s)
s = (*e) ? e+1 : e;
}
+
bd->bi_intfreq = clock_mhz; /* Internal Freq, in MHz */
bd->bi_busfreq = get_bus_freq(clock_mhz); /* Bus Freq, in MHz */
bd->bi_baudrate = baudrate; /* Console Baudrate */
static uchar *flash_addr = environment;
#endif /* ENV, FLASH */
#endif /* CFG_FLASH_ENV_ADDR */
-#endif /* NVRAM_ENV */
+#endif /* CONFIG_NVRAM_ENV */
static uchar *envmatch (uchar *, uchar *);
#if defined(CFG_FLASH_ENV_ADDR)
}
flash_sect_protect (1, sector_flash_addr, sector_flash_addr+sector_flash_size-1);
-#else /* ! CONFIG_CPCI405 */
+#else /* ! CONFIG_4xx */
#ifndef CFG_FLASH_ENV_ADDR
env_init();
#undef env_size
#endif /* CFG_FLASH_ENV_BUF */
-#endif /* CONFIG_CPCI405 */
+#endif /* CONFIG_4xx */
}
#endif /* CFG_CMD_ENV + CFG_CMD_FLASH */
#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~(CFG_CMD_ENV))
+
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
*/
/*-----------------------------------------------------------------------
- * Turn on use of board support functions board_xxx()
+ * Physical memory map as defined by the MBX PGM
*/
-#define CFG_HAVE_BSP
-
#define CFG_IMMR 0xFA200000 /* Internal Memory Mapped Register*/
+#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM */
+#define CFG_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */
#define CFG_CSR_BASE 0xFA100000 /* Control/Status Registers */
-#define CFG_CSR_OR 0xffe00000 /* w/o speed dependent flags!! */
#define CFG_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */
#define CFG_PCIMEM_OR 0xA0000108
#define CFG_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */
#define CFG_PCIBRIDGE_OR 0xFFFF0108
-#define CFG_BOOTROM_BASE 0xFE000000 /* Boot ROM Base */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
#else
#define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
#endif
+#undef CFG_MONITOR_BASE 0x200000 /* to run ppcboot from RAM */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
#define CFG_FLASH_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
#define CFG_FLASH_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
+/*-----------------------------------------------------------------------
+ * NVRAM Configuration
+ *
+ * Note: the MBX is special because there is already a firmware on this
+ * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
+ * access the NVRAM at the offset 0x1000.
+ */
+#define CONFIG_NVRAM_ENV 1 /* turn on NVRAM env feature */
+#define CFG_NVRAM_VAR_ADDR (CFG_NVRAM_BASE + 0x1000)
+#define CFG_NVRAM_ENV_SIZE 0x0ffc
+#define CFG_NVRAM_VAR_CRC_ADDR (CFG_NVRAM_VAR_ADDR + CFG_NVRAM_ENV_SIZE)
+
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
#define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
/*
* Low Level Configuration Settings
* (address mappings, register initial values, etc.)
void reset_phy (void);
#endif
+#ifdef CONFIG_MBX
+/* $(BOARD)/mbx8xx.c */
+void mbx_init (void);
+void board_get_enetaddr (uchar *addr);
+void board_serial_init (void);
+void board_ether_init (void);
+#endif
+
/* $(CPU)/serial.c */
void serial_init (ulong, int);
void serial_setbrg (ulong, int);
# MBX8xx boards
#
-TEXT_BASE = 0xfe000000
-//TEXT_BASE = 0x00200000
+//TEXT_BASE = 0xfe000000
+TEXT_BASE = 0x00200000
* MA 02111-1307 USA
*/
-/* bits for CR1 and SR1 */
+/* bits for control register #2 / status register #2 */
#define CSR1_ETEN 0x80 /* Ethernet Transceiver Enabled */
#define CSR1_ELEN 0x40 /* Ethernet XCVR in Internal Loopback */
#define CSR1_EAEN 0x20 /* Auto selection TP/AUI Enabled */
#define CSR1_COM1EN 0x02 /* COM1 signals routed to RS232 Transceiver */
#define CSR1_XCVRDIS 0x01 /* Onboard RS232 Transceiver Disabled */
-/* FIXME - CSR2 bits not yet defined */
+/* bits for control register #2 */
+#define CR2_VDDSEL 0x03 /* PCMCIA Supply Voltage */
+#define CR2_VPPSEL 0x0c /* PCMCIA Programming Voltage */
+#define CR2_BRDFAIL 0x10 /* Board fail */
+#define CR2_SWS1 0x20 /* Software Status #2 LED */
+#define CR2_SWS2 0x40 /* Software Status #2 LED */
+#define CR2_QSPANRST 0x80 /* Reset QSPAN */
+
+/* bits for status register #2 */
+#define SR2_VDDSEL 0x03 /* PCMCIA Supply Voltage */
+#define SR2_VPPSEL 0x0c /* PCMCIA Programming Voltage */
+#define SR2_BATGD 0x10 /* Low Voltage indication for onboard bat */
+#define SR2_NVBATGD 0x20 /* Low Voltage indication for NVRAM */
+#define SR2_RDY 0x40 /* Flash programming status bit */
+#define SR2_FT 0x80 /* Reserved for Factory test purposes */
#define MBX_CSR1 (*((uchar *)CFG_CSR_BASE))
#define MBX_CSR2 (*((uchar *)CFG_CSR_BASE + 1))
flash_info[i].flash_id = FLASH_UNKNOWN;
}
- /* Static FLASH Bank configuration here - FIXME XXX */
-
totsize = 0;
addr = 0xfc000000;
for(i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
/* ------------------------------------------------------------------------- */
-const uint sdram_table_40[] =
+static const uint sdram_table_40[] =
{
/* DRAM - single read. (offset 0 in upm RAM)
*/
0xFFFFC007, 0xFFFFC007, 0xFFFFC007, 0xFFFFC007,
};
-const uint sdram_table_50[] =
+static const uint sdram_table_50[] =
{
/* DRAM - single read. (offset 0 in upm RAM)
*/
/* ------------------------------------------------------------------------- */
static unsigned int get_reffreq(void);
+static unsigned int board_get_cpufreq(void);
-void board_init(void)
+void mbx_init(void)
{
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
unsigned int speed, refclock, plprcr;
-
- /*
- * Reset CPM
- */
- immr->im_cpm.cp_cpcr = CPM_CR_RST;
- do {
- __asm__ volatile ("eieio");
- } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
- /* SYPCR - contains watchdog control (11-9) */
- immr->im_siu_conf.sc_sypcr = CFG_SYPCR;
-
+#if 0
/* SIUMCR - contains debug pin configuration (11-6) */
immr->im_siu_conf.sc_siumcr = CFG_SIUMCR;
/* system clock and reset control register */
immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
immr->im_clkrst.car_sccr = CFG_SCCR;
+#endif
/* real-time clock status and control register */
immr->im_sitk.sitk_rtcsck = KAPWR_KEY;
immr->im_sit.sit_rtcsc = 0x00C3;
-
+
/*
* Prepare access to i2c bus. The MBX offers 3 devices on the i2c
* bus:
switch(speed / 1000000)
{
case 40:
- memctl->memc_br4 = CFG_CSR_BASE | 0x401;
- memctl->memc_or4 = CFG_CSR_OR | 0x920;
+ memctl->memc_br4 = CFG_NVRAM_BASE | 0x401;
+ memctl->memc_or4 = CFG_NVRAM_OR | 0x920;
break;
case 50:
- memctl->memc_br4 = CFG_CSR_BASE | 0x401;
- memctl->memc_or4 = CFG_CSR_OR | 0x930;
+ memctl->memc_br4 = CFG_NVRAM_BASE | 0x401;
+ memctl->memc_or4 = CFG_NVRAM_OR | 0x930;
break;
default:
hang();
MBX_CSR1 |= CSR1_ETEN | CSR1_TPEN | CSR1_FDDIS;
}
-unsigned int board_get_cpufreq(void)
+static unsigned int board_get_cpufreq(void)
{
vpd_packet_t *packet;
return *((ulong*)packet->data);
}
-unsigned int board_get_busfreq(unsigned int cpufreq)
-{
- vpd_packet_t *packet;
-
- packet = vpd_find_packet(VPD_PID_ECS);
- return *((ulong*)packet->data);
-}
-
static unsigned int get_reffreq(void)
{
vpd_packet_t *packet;
serial_putc (packet->data[i]);
}
serial_putc (')');
+
+ if (!(MBX_CSR2 & SR2_BATGD))
+ printf("\n *** Warning: Low Battery Status - On-Board Battery ***");
+ if (!(MBX_CSR2 & SR2_NVBATGD))
+ printf("\n *** Warning: Low Battery Status - NVRAM Battery ***");
+
serial_putc ('\n');
return (1);
.plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
mpc8xx/start.o (.text)
*(.text)
-
- . = env_offset;
- common/environment.o(.text)
-
*(.fixup)
*(.got1)
}
iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
#endif
/* Initialize Port B IIC pins */
- cp->cp_pbodr |= 0x00000030;
- cp->cp_pbdir |= 0x00000030;
cp->cp_pbpar |= 0x00000030;
+ cp->cp_pbdir |= 0x00000030;
+ cp->cp_pbodr |= 0x00000030;
i2c->i2c_i2mod = 0x04; /* filter clock */
i2c->i2c_i2add = 0x34; /* select an arbitrary (unique) address */
void
cpu_init_f (volatile immap_t *immr)
{
+#ifndef CONFIG_MBX
volatile memctl8xx_t *memctl = &immr->im_memctl;
ulong reg;
+#endif
/* SYPCR - contains watchdog control (11-9) */
immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
+#ifndef CONFIG_MBX /* MBX board does things different */
+
/* If CFG_PLPRCR (set in the various *_config.h files) tries to
* set the MF field, then just copy CFG_PLPRCR over car_plprcr,
* otherwise OR in CFG_PLPRCR so we do not change the currentMF
memctl->memc_br3 = CFG_BR3_PRELIM;
#endif
+#endif /* ! CONFIG_MBX */
+
+
/*
* Reset CPM
*/
do { /* Spin until command processed */
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
+
+#ifdef CONFIG_MBX
+ /*
+ * on the MBX, things are a little bit different:
+ * - we need to read the VPD to get board information
+ * - the plprcr is set up dynamically
+ * - the memory controller is set up dynamically
+ */
+ mbx_init();
+#endif /* CONFIG_MBX */
}
/*
__asm__ ("eieio");
} while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
+ /*
+ * Mask all Events in SCCM - we use polling mode
+ */
+ immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0;
+
/*
* Clear Events in SCCE -- Clear bits by writing 1's
*/
immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0);
-
/*
* Initialize GSMR High 32-Bits
* Settings: Normal Mode
*/
- immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0;
+ immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0;
/*
* Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
* CRC = 32-Bit CCITT
* NIB = Begin searching for SFD 22 bits after RENA
* BRO = Reject broadcast packets
- * PROMISCOUS = Catch all packetsregardless of dest. MAC adress
+ * PROMISCOUS = Catch all packets regardless of dest. MAC adress
*/
- immr->im_cpm.cp_scc[SCC_ENET].scc_pmsr = (SCC_PMSR_ENCRC | SCC_PMSR_NIB22
+ immr->im_cpm.cp_scc[SCC_ENET].scc_pmsr = (SCC_PMSR_ENCRC | SCC_PMSR_NIB22
/* | SCC_PMSR_BRO | SCC_PMSR_PRO */);
/*
*((uint *) BCSR1) &= ~BCSR1_ETHEN;
#endif /* FADS860T */
+#ifdef CONFIG_MBX
+ board_ether_init();
+#endif
+
/*
* Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
*/
#endif
#endif
+#if defined(CONFIG_MBX)
+ board_serial_init();
+ dpaddr = CFG_DPRAMSERIAL;
+#else /* ! CONFIG_MBX */
+
/* Allocate space for two buffer descriptors in the DP ram.
* For now, this address seems OK, but it may have to
* change with newer versions of the firmware.
dpaddr = 0x800;
+#endif /* CONFIG_MBX */
+
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
projects / users / rw / ppcboot.git / commitdiff