},
 };
 
+static struct clk_branch gcc_qdss_at_clk = {
+       .halt_reg = 0x29024,
+       .clkr = {
+               .enable_reg = 0x29024,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "gcc_qdss_at_clk",
+                       .parent_hws = (const struct clk_hw *[]){
+                               &qdss_at_clk_src.clkr.hw },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct clk_branch gcc_qdss_dap_clk = {
        .halt_reg = 0x29084,
        .clkr = {
        [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
        [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
        [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+       [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
        [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
        [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
        [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,