drm/i915/reg: use the correct register to access SAGV block time

Wrong register address is used to read the SAG block time. Fix
the register address according to the bspec.

Bspec: 64608

Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230323114426.41136-3-vinod.govindapillai@intel.com

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3abfda4c7a3fa170c0af1a7c6a866947acdbce3b..f0f7b578b7269409acab9a328b954e17ae74bcc0 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7740,7 +7740,7 @@ enum skl_power_gate {
 #define  MTL_LATENCY_LEVEL_EVEN_MASK   REG_GENMASK(12, 0)
 #define  MTL_LATENCY_LEVEL_ODD_MASK    REG_GENMASK(28, 16)
 
-#define MTL_LATENCY_SAGV               _MMIO(0x4578b)
+#define MTL_LATENCY_SAGV               _MMIO(0x4578c)
 #define   MTL_LATENCY_QCLK_SAGV                REG_GENMASK(12, 0)
 
 #define MTL_MEM_SS_INFO_GLOBAL                 _MMIO(0x45700)