const struct amdgpu_asic_funcs  *asic_funcs;
        bool                            shutdown;
        bool                            need_dma32;
+       bool                            need_swiotlb;
        bool                            accel_working;
        struct work_struct              reset_work;
        struct notifier_block           acpi_nb;
 
        }
 
 #ifdef CONFIG_SWIOTLB
-       if (swiotlb_nr_tbl()) {
+       if (adev->need_swiotlb && swiotlb_nr_tbl()) {
                return ttm_dma_populate(>t->ttm, adev->dev, ctx);
        }
 #endif
        adev = amdgpu_ttm_adev(ttm->bdev);
 
 #ifdef CONFIG_SWIOTLB
-       if (swiotlb_nr_tbl()) {
+       if (adev->need_swiotlb && swiotlb_nr_tbl()) {
                ttm_dma_unpopulate(>t->ttm, adev->dev);
                return;
        }
        count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
 
 #ifdef CONFIG_SWIOTLB
-       if (!swiotlb_nr_tbl())
+       if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
                --count;
 #endif
 
 
  */
 #include <linux/firmware.h>
 #include <drm/drmP.h>
+#include <drm/drm_cache.h>
 #include "amdgpu.h"
 #include "gmc_v6_0.h"
 #include "amdgpu_ucode.h"
                pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
                dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
        }
+       adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
 
        r = gmc_v6_0_init_microcode(adev);
        if (r) {
 
  */
 #include <linux/firmware.h>
 #include <drm/drmP.h>
+#include <drm/drm_cache.h>
 #include "amdgpu.h"
 #include "cikd.h"
 #include "cik.h"
                pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
                pr_warn("amdgpu: No coherent DMA available\n");
        }
+       adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
 
        r = gmc_v7_0_init_microcode(adev);
        if (r) {
 
  */
 #include <linux/firmware.h>
 #include <drm/drmP.h>
+#include <drm/drm_cache.h>
 #include "amdgpu.h"
 #include "gmc_v8_0.h"
 #include "amdgpu_ucode.h"
         */
        adev->need_dma32 = false;
        dma_bits = adev->need_dma32 ? 32 : 40;
+       adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
        r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
        if (r) {
                adev->need_dma32 = true;
                pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
                pr_warn("amdgpu: No coherent DMA available\n");
        }
+       adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
 
        r = gmc_v8_0_init_microcode(adev);
        if (r) {
 
  *
  */
 #include <linux/firmware.h>
+#include <drm/drm_cache.h>
 #include "amdgpu.h"
 #include "gmc_v9_0.h"
 #include "amdgpu_atomfirmware.h"
                pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
                printk(KERN_WARNING "amdgpu: No coherent DMA available.\n");
        }
+       adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
 
        r = gmc_v9_0_mc_init(adev);
        if (r)