powerpc/64s: Remove spurious fault flushing for NMMU

Commit 6d8278c414cb2 ("powerpc/64s/radix: do not flush TLB on spurious
fault") removed the TLB flush for spurious faults, except when a
coprocessor (nest MMU) maps the address space. This is not needed
because the NMMU workaround in the PTE permission upgrade paths
prevents PTEs existing with less restrictive access permissions than
their corresponding TLB entries have.

Remove it and replace with a comment.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220525022358.780745-4-npiggin@gmail.com

diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush.h b/arch/powerpc/include/asm/book3s/64/tlbflush.h
index d2e80f178b6d66b59dfa0262179dec1c19cc5bf8..206f920fe5b9655f979d001ef4b893648babe2d0 100644 (file)
--- a/arch/powerpc/include/asm/book3s/64/tlbflush.h
+++ b/arch/powerpc/include/asm/book3s/64/tlbflush.h
@@ -138,9 +138,29 @@ static inline void flush_all_mm(struct mm_struct *mm)
 static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma,
                                                unsigned long address)
 {
-       /* See ptep_set_access_flags comment */
-       if (atomic_read(&vma->vm_mm->context.copros) > 0)
-               flush_tlb_page(vma, address);
+       /*
+        * Book3S 64 does not require spurious fault flushes because the PTE
+        * must be re-fetched in case of an access permission problem. So the
+        * only reason for a spurious fault should be concurrent modification
+        * to the PTE, in which case the PTE will eventually be re-fetched by
+        * the MMU when it attempts the access again.
+        *
+        * See: Power ISA Version 3.1B, 6.10.1.2 Modifying a Translation Table
+        * Entry, Setting a Reference or Change Bit or Upgrading Access
+        * Authority (PTE Subject to Atomic Hardware Updates):
+        *
+        * "If the only change being made to a valid PTE that is subject to
+        *  atomic hardware updates is to set the Reference or Change bit to
+        *  1 or to upgrade access authority, a simpler sequence suffices
+        *  because the translation hardware will refetch the PTE if an
+        *  access is attempted for which the only problems were reference
+        *  and/or change bits needing to be set or insufficient access
+        *  authority."
+        *
+        * The nest MMU in POWER9 does not perform this PTE re-fetch, but
+        * it avoids the spurious fault problem by flushing the TLB before
+        * upgrading PTE permissions, see radix__ptep_set_access_flags.
+        */
 }
 
 extern bool tlbie_capable;