]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
drm/amdgpu: correct cp doorbell range
authorJack Xiao <Jack.Xiao@amd.com>
Tue, 12 Apr 2022 20:17:41 +0000 (16:17 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 4 May 2022 14:43:53 +0000 (10:43 -0400)
1. move MES doorbell inside the mec doorbell range,
   for mes belongs to mec block
2. setting the correct gfx/mec doorbell range, so that
   fw can correctly detect gfx/compute work load to enter/exit
   power saving state.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Tested-and-acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h
drivers/gpu/drm/amd/amdgpu/nv.c
drivers/gpu/drm/amd/amdgpu/soc21.c

index 2d9485e67125c8c79d95d1910ac75b45b095b3c0..7199b6b0be814d6fec13779f739194fe133a31fc 100644 (file)
@@ -52,6 +52,8 @@ struct amdgpu_doorbell_index {
        uint32_t userqueue_end;
        uint32_t gfx_ring0;
        uint32_t gfx_ring1;
+       uint32_t gfx_userqueue_start;
+       uint32_t gfx_userqueue_end;
        uint32_t sdma_engine[8];
        uint32_t mes_ring0;
        uint32_t mes_ring1;
@@ -175,12 +177,15 @@ typedef enum _AMDGPU_NAVI10_DOORBELL_ASSIGNMENT
        AMDGPU_NAVI10_DOORBELL_MEC_RING5                = 0x008,
        AMDGPU_NAVI10_DOORBELL_MEC_RING6                = 0x009,
        AMDGPU_NAVI10_DOORBELL_MEC_RING7                = 0x00A,
-       AMDGPU_NAVI10_DOORBELL_USERQUEUE_START          = 0x00B,
+       AMDGPU_NAVI10_DOORBELL_MES_RING0                = 0x00B,
+       AMDGPU_NAVI10_DOORBELL_MES_RING1                = 0x00C,
+       AMDGPU_NAVI10_DOORBELL_USERQUEUE_START          = 0x00D,
        AMDGPU_NAVI10_DOORBELL_USERQUEUE_END            = 0x08A,
        AMDGPU_NAVI10_DOORBELL_GFX_RING0                = 0x08B,
        AMDGPU_NAVI10_DOORBELL_GFX_RING1                = 0x08C,
-       AMDGPU_NAVI10_DOORBELL_MES_RING0                = 0x090,
-       AMDGPU_NAVI10_DOORBELL_MES_RING1                = 0x091,
+       AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START      = 0x08D,
+       AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END        = 0x0FF,
+
        /* SDMA:256~335*/
        AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0             = 0x100,
        AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1             = 0x10A,
index 8cf1a7f8a632cbaf9bc197f21de8b1218ec75c00..8ecfd66c4cee6847ca86d0d44741a14e82da9702 100644 (file)
@@ -607,6 +607,10 @@ static void nv_init_doorbell_index(struct amdgpu_device *adev)
        adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
        adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
        adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
+       adev->doorbell_index.gfx_userqueue_start =
+               AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
+       adev->doorbell_index.gfx_userqueue_end =
+               AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
        adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
        adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
        adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
index 68985a59a6a68641b8bd719679f3d7f26da904db..80b558f649e0e2e419b57c9af959e011a45c229d 100644 (file)
@@ -409,6 +409,10 @@ static void soc21_init_doorbell_index(struct amdgpu_device *adev)
        adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
        adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
        adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
+       adev->doorbell_index.gfx_userqueue_start =
+               AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
+       adev->doorbell_index.gfx_userqueue_end =
+               AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
        adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
        adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
        adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;