net: dsa: qca8k: move port config to dedicated struct

Move ports related config to dedicated struct to keep things organized.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 296633147f466ebd7d99f379be9d3c6c74125406..bf58d4d1ae9b43f03776a047d62b475010d9abf6 100644 (file)
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1019,7 +1019,7 @@ qca8k_parse_port_config(struct qca8k_priv *priv)
                                delay = 3;
                        }
 
-                       priv->rgmii_tx_delay[cpu_port_index] = delay;
+                       priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay;
 
                        delay = 0;
 
@@ -1035,7 +1035,7 @@ qca8k_parse_port_config(struct qca8k_priv *priv)
                                delay = 3;
                        }
 
-                       priv->rgmii_rx_delay[cpu_port_index] = delay;
+                       priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay;
 
                        /* Skip sgmii parsing for rgmii* mode */
                        if (mode == PHY_INTERFACE_MODE_RGMII ||
@@ -1045,17 +1045,17 @@ qca8k_parse_port_config(struct qca8k_priv *priv)
                                break;
 
                        if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge"))
-                               priv->sgmii_tx_clk_falling_edge = true;
+                               priv->ports_config.sgmii_tx_clk_falling_edge = true;
 
                        if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge"))
-                               priv->sgmii_rx_clk_falling_edge = true;
+                               priv->ports_config.sgmii_rx_clk_falling_edge = true;
 
                        if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) {
-                               priv->sgmii_enable_pll = true;
+                               priv->ports_config.sgmii_enable_pll = true;
 
                                if (priv->switch_id == QCA8K_ID_QCA8327) {
                                        dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling");
-                                       priv->sgmii_enable_pll = false;
+                                       priv->ports_config.sgmii_enable_pll = false;
                                }
 
                                if (priv->switch_revision < 2)
@@ -1281,15 +1281,15 @@ qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, int cpu_port_inde
         * not enabled. With ID or TX/RXID delay is enabled and set
         * to the default and recommended value.
         */
-       if (priv->rgmii_tx_delay[cpu_port_index]) {
-               delay = priv->rgmii_tx_delay[cpu_port_index];
+       if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) {
+               delay = priv->ports_config.rgmii_tx_delay[cpu_port_index];
 
                val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
                        QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
        }
 
-       if (priv->rgmii_rx_delay[cpu_port_index]) {
-               delay = priv->rgmii_rx_delay[cpu_port_index];
+       if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) {
+               delay = priv->ports_config.rgmii_rx_delay[cpu_port_index];
 
                val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
                        QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
@@ -1397,7 +1397,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
 
                val |= QCA8K_SGMII_EN_SD;
 
-               if (priv->sgmii_enable_pll)
+               if (priv->ports_config.sgmii_enable_pll)
                        val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
                               QCA8K_SGMII_EN_TX;
 
@@ -1425,10 +1425,10 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
                val = 0;
 
                /* SGMII Clock phase configuration */
-               if (priv->sgmii_rx_clk_falling_edge)
+               if (priv->ports_config.sgmii_rx_clk_falling_edge)
                        val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
 
-               if (priv->sgmii_tx_clk_falling_edge)
+               if (priv->ports_config.sgmii_tx_clk_falling_edge)
                        val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
 
                if (val)

diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index c5ca6277b45b522cc51b92ddb71903b43da457d8..e10571a398c98a1cabec9ca85ab036e9589bef16 100644 (file)
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -270,15 +270,19 @@ enum {
        QCA8K_CPU_PORT6,
 };
 
-struct qca8k_priv {
-       u8 switch_id;
-       u8 switch_revision;
+struct qca8k_ports_config {
        bool sgmii_rx_clk_falling_edge;
        bool sgmii_tx_clk_falling_edge;
        bool sgmii_enable_pll;
        u8 rgmii_rx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
        u8 rgmii_tx_delay[QCA8K_NUM_CPU_PORTS]; /* 0: CPU port0, 1: CPU port6 */
+};
+
+struct qca8k_priv {
+       u8 switch_id;
+       u8 switch_revision;
        bool legacy_phy_port_mapping;
+       struct qca8k_ports_config ports_config;
        struct regmap *regmap;
        struct mii_bus *bus;
        struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];