return -EINVAL;
 
        mux_confs = (struct rza1_mux_conf *)func->data;
-       for (i = 0; i < grp->num_pins; ++i) {
+       for (i = 0; i < grp->grp.npins; ++i) {
                int ret;
 
                ret = rza1_pin_mux_single(rza1_pctl, &mux_confs[i]);
 
 
        psel_val = func->data;
 
-       for (i = 0; i < grp->num_pins; ++i) {
+       for (i = 0; i < grp->grp.npins; ++i) {
                dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n",
-                       port_names[RZA2_PIN_ID_TO_PORT(grp->pins[i])],
-                       RZA2_PIN_ID_TO_PIN(grp->pins[i]),
+                       port_names[RZA2_PIN_ID_TO_PORT(grp->grp.pins[i])],
+                       RZA2_PIN_ID_TO_PIN(grp->grp.pins[i]),
                        psel_val[i]);
                rza2_set_pin_function(
                        priv->base,
-                       RZA2_PIN_ID_TO_PORT(grp->pins[i]),
-                       RZA2_PIN_ID_TO_PIN(grp->pins[i]),
+                       RZA2_PIN_ID_TO_PORT(grp->grp.pins[i]),
+                       RZA2_PIN_ID_TO_PIN(grp->grp.pins[i]),
                        psel_val[i]);
        }
 
 
                return -EINVAL;
 
        psel_val = func->data;
-       pins = group->pins;
+       pins = group->grp.pins;
 
-       for (i = 0; i < group->num_pins; i++) {
+       for (i = 0; i < group->grp.npins; i++) {
                unsigned int *pin_data = pctrl->desc.pins[pins[i]].drv_data;
                u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data);
                u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]);
 
                return -EINVAL;
 
        psel_val = func->data;
-       pins = group->pins;
+       pins = group->grp.pins;
 
-       for (i = 0; i < group->num_pins; i++) {
+       for (i = 0; i < group->grp.npins; i++) {
                dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n",
                        RZV2M_PIN_ID_TO_PORT(pins[i]), RZV2M_PIN_ID_TO_PIN(pins[i]),
                        psel_val[i]);