drm/msm/dpu: intf timing path for displayport

Calculate the correct timings for displayport, from downstream driver.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 64f556d693dda150ee983e48e76d73181a23f4b7..6f0f54588124bf72cdf34947217eb4a9194fb58b 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -107,11 +107,6 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
        display_v_end = ((vsync_period - p->v_front_porch) * hsync_period) +
        p->hsync_skew - 1;
 
-       if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) {
-               display_v_start += p->hsync_pulse_width + p->h_back_porch;
-               display_v_end -= p->h_front_porch;
-       }
-
        hsync_start_x = p->h_back_porch + p->hsync_pulse_width;
        hsync_end_x = hsync_period - p->h_front_porch - 1;
 
@@ -144,10 +139,25 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx,
        hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width;
        display_hctl = (hsync_end_x << 16) | hsync_start_x;
 
+       if (ctx->cap->type == INTF_EDP || ctx->cap->type == INTF_DP) {
+               active_h_start = hsync_start_x;
+               active_h_end = active_h_start + p->xres - 1;
+               active_v_start = display_v_start;
+               active_v_end = active_v_start + (p->yres * hsync_period) - 1;
+
+               display_v_start += p->hsync_pulse_width + p->h_back_porch;
+
+               active_hctl = (active_h_end << 16) | active_h_start;
+               display_hctl = active_hctl;
+       }
+
        den_polarity = 0;
        if (ctx->cap->type == INTF_HDMI) {
                hsync_polarity = p->yres >= 720 ? 0 : 1;
                vsync_polarity = p->yres >= 720 ? 0 : 1;
+       } else if (ctx->cap->type == INTF_DP) {
+               hsync_polarity = p->hsync_polarity;
+               vsync_polarity = p->vsync_polarity;
        } else {
                hsync_polarity = 0;
                vsync_polarity = 0;