drm/i915/gt: Drop read from GEN8_L3CNTLREG in ICL workaround

Now that non-masked registers are already read before programming the
context reads, the additional read became redudant, so remove it.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20230630203509.1635216-5-lucas.demarchi@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 0a9c3be4817cfbfb9fb4f62ee25e8a56fc12a1cb..b07f84c3fa210e093583afdf0b1e058cb99b924e 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -637,10 +637,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
                                     struct i915_wa_list *wal)
 {
        /* Wa_1406697149 (WaDisableBankHangMode:icl) */
-       wa_write(wal,
-                GEN8_L3CNTLREG,
-                intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
-                GEN8_ERRDETBCTRL);
+       wa_write(wal, GEN8_L3CNTLREG, GEN8_ERRDETBCTRL);
 
        /* WaForceEnableNonCoherent:icl
         * This is not the same workaround as in early Gen9 platforms, where