net/mlx5e: Add HW cacheline start padding

Enable HW cacheline start padding and align RX WQE size to cacheline
while considering HW start padding. Also, fix dma_unmap call to use
the correct SKB data buffer size.

Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
index 22b2665e0328aace08d644d74ad2d210c23ffd06..1c62af69ca2962f737cf05b14bdc5db744b442a9 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
@@ -309,12 +309,15 @@ static int mlx5e_create_rq(struct mlx5e_channel *c,
 
        rq->wqe_sz = (priv->params.lro_en) ? priv->params.lro_wqe_sz :
                                             MLX5E_SW2HW_MTU(priv->netdev->mtu);
+       rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz + MLX5E_NET_IP_ALIGN);
 
        for (i = 0; i < wq_sz; i++) {
                struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
+               u32 byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 
                wqe->data.lkey       = c->mkey_be;
-               wqe->data.byte_count = cpu_to_be32(rq->wqe_sz);
+               wqe->data.byte_count =
+                       cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
        }
 
        rq->pdev    = c->pdev;

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
index ce1317cdabd751c6b5240375ae8d39b51e96c9d0..06e7c744ed4a6071de2643a9c7ae3df0eaa3391b 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c
@@ -45,18 +45,18 @@ static inline int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq,
        if (unlikely(!skb))
                return -ENOMEM;
 
-       skb_reserve(skb, MLX5E_NET_IP_ALIGN);
-
        dma_addr = dma_map_single(rq->pdev,
                                  /* hw start padding */
-                                 skb->data - MLX5E_NET_IP_ALIGN,
-                                 /* hw   end padding */
+                                 skb->data,
+                                 /* hw end padding */
                                  rq->wqe_sz,
                                  DMA_FROM_DEVICE);
 
        if (unlikely(dma_mapping_error(rq->pdev, dma_addr)))
                goto err_free_skb;
 
+       skb_reserve(skb, MLX5E_NET_IP_ALIGN);
+
        *((dma_addr_t *)skb->cb) = dma_addr;
        wqe->data.addr = cpu_to_be64(dma_addr + MLX5E_NET_IP_ALIGN);
 
@@ -217,7 +217,7 @@ bool mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
 
                dma_unmap_single(rq->pdev,
                                 *((dma_addr_t *)skb->cb),
-                                skb_end_offset(skb),
+                                rq->wqe_sz,
                                 DMA_FROM_DEVICE);
 
                if (unlikely((cqe->op_own >> 4) != MLX5_CQE_RESP_SEND)) {

diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index b2c43508a73711842caa4549f3ae4dc98d04aea3..b943cd9e2097326466919eccc83a25bd93b2ba58 100644 (file)
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -131,6 +131,10 @@ enum {
        MLX5_INLINE_SEG = 0x80000000,
 };
 
+enum {
+       MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
+};
+
 enum {
        MLX5_MIN_PKEY_TABLE_SIZE = 128,
        MLX5_MAX_LOG_PKEY_TABLE  = 5,