drm/amd: Disable PP_PCIE_DPM_MASK when dynamic speed switching not supported

Rather than individual ASICs checking for the quirk, set the quirk at the
driver level.

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9340e8dc0413f905bb64fbc03694c7803f984619..286f3f60c25b763b0a1ebd2877a19d6bc588b7d9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2315,6 +2315,8 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
                adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
        if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
                adev->pm.pp_feature &= ~PP_OVERDRIVE_MASK;
+       if (!amdgpu_device_pcie_dynamic_switching_supported())
+               adev->pm.pp_feature &= ~PP_PCIE_DPM_MASK;
 
        total = true;
        for (i = 0; i < adev->num_ip_blocks; i++) {

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index 5a2371484a58c551217a2fe4d1e4f2924e2a0756..11372fcc59c8fe8daa93c750b779f8a9d0bbe3bf 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -1823,9 +1823,7 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 
        data->mclk_dpm_key_disabled = hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true;
        data->sclk_dpm_key_disabled = hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true;
-       data->pcie_dpm_key_disabled =
-               !amdgpu_device_pcie_dynamic_switching_supported() ||
-               !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);
+       data->pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);
        /* need to set voltage control types before EVV patching */
        data->voltage_control = SMU7_VOLTAGE_CONTROL_NONE;
        data->vddci_control = SMU7_VOLTAGE_CONTROL_NONE;

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 090249b6422ac1f89a2a7f03469b8aff37aa4130..97a5c9b3e941a00dccdba7bb467e27348dd9930f 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -2115,7 +2115,7 @@ static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
        min_lane_width = min_lane_width > max_lane_width ?
                         max_lane_width : min_lane_width;
 
-       if (!amdgpu_device_pcie_dynamic_switching_supported()) {
+       if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
                pcie_table->pcie_gen[0] = max_gen_speed;
                pcie_table->pcie_lane[0] = max_lane_width;
        } else {

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index ba3ef3c2918a9632293af85e85acedc06d0d4d93..3917ae5e681a3088f959d1f2ad2daefd02e896f1 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2438,7 +2438,7 @@ int smu_v13_0_update_pcie_parameters(struct smu_context *smu,
        uint32_t smu_pcie_arg;
        int ret, i;
 
-       if (!amdgpu_device_pcie_dynamic_switching_supported()) {
+       if (!(smu->adev->pm.pp_feature & PP_PCIE_DPM_MASK)) {
                if (pcie_table->pcie_gen[num_of_levels - 1] < pcie_gen_cap)
                        pcie_gen_cap = pcie_table->pcie_gen[num_of_levels - 1];