void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
                                   uint32_t mask,
                                   uint32_t bits);
-void
-ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
-void
-ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
+void ilk_update_display_irq(struct drm_i915_private *dev_priv,
+                           uint32_t interrupt_mask,
+                           uint32_t enabled_irq_mask);
+static inline void
+ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
+{
+       ilk_update_display_irq(dev_priv, bits, bits);
+}
+static inline void
+ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
+{
+       ilk_update_display_irq(dev_priv, bits, 0);
+}
 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
                                  uint32_t interrupt_mask,
                                  uint32_t enabled_irq_mask);
 
  * @interrupt_mask: mask of interrupt bits to update
  * @enabled_irq_mask: mask of interrupt bits to enable
  */
-static void ilk_update_display_irq(struct drm_i915_private *dev_priv,
-                                  uint32_t interrupt_mask,
-                                  uint32_t enabled_irq_mask)
+void ilk_update_display_irq(struct drm_i915_private *dev_priv,
+                           uint32_t interrupt_mask,
+                           uint32_t enabled_irq_mask)
 {
        uint32_t new_val;
 
        }
 }
 
-void
-ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
-{
-       ilk_update_display_irq(dev_priv, mask, mask);
-}
-
-void
-ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
-{
-       ilk_update_display_irq(dev_priv, mask, 0);
-}
-
 /**
  * ilk_update_gt_irq - update GTIMR
  * @dev_priv: driver private
                                                     DE_PIPE_VBLANK(pipe);
 
        spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-       ironlake_enable_display_irq(dev_priv, bit);
+       ilk_enable_display_irq(dev_priv, bit);
        spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 
        return 0;
                                                     DE_PIPE_VBLANK(pipe);
 
        spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
-       ironlake_disable_display_irq(dev_priv, bit);
+       ilk_disable_display_irq(dev_priv, bit);
        spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 }
 
                 * setup is guaranteed to run in single-threaded context. But we
                 * need it to make the assert_spin_locked happy. */
                spin_lock_irq(&dev_priv->irq_lock);
-               ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
+               ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
                spin_unlock_irq(&dev_priv->irq_lock);
        }
 
 
                                          DE_PIPEB_FIFO_UNDERRUN;
 
        if (enable)
-               ironlake_enable_display_irq(dev_priv, bit);
+               ilk_enable_display_irq(dev_priv, bit);
        else
-               ironlake_disable_display_irq(dev_priv, bit);
+               ilk_disable_display_irq(dev_priv, bit);
 }
 
 static void ivybridge_check_fifo_underruns(struct intel_crtc *crtc)
                if (!ivb_can_enable_err_int(dev))
                        return;
 
-               ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
+               ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
        } else {
-               ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
+               ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
 
                if (old &&
                    I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {