arm64: zynqmp: Add coresight cpu debug support

Add coresight debug support to the device tree. This can be useful when
panicking, especially when a core is hung in EL3.

Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Link: https://lore.kernel.org/r/20240503153422.1958812-1-sean.anderson@linux.dev
Signed-off-by: Michal Simek <michal.simek@amd.com>

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
index dd4569e7bd95801197b602aeda74b278f784c855..60d1b1acf9a0307d118bb70562cfa10c1800a5ea 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
@@ -70,6 +70,22 @@
        clocks = <&zynqmp_clk ACPU>;
 };
 
+&cpu0_debug {
+       clocks = <&zynqmp_clk DBF_FPD>;
+};
+
+&cpu1_debug {
+       clocks = <&zynqmp_clk DBF_FPD>;
+};
+
+&cpu2_debug {
+       clocks = <&zynqmp_clk DBF_FPD>;
+};
+
+&cpu3_debug {
+       clocks = <&zynqmp_clk DBF_FPD>;
+};
+
 &fpd_dma_chan1 {
        clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
 };

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 0b730f6eeef1c4353b8a388b0a94fb3983df7397..95796d6b5515baae8895203e293f3ae6729861ad 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -387,6 +387,34 @@
                        };
                };
 
+               cpu0_debug: debug@fec10000 {
+                       compatible = "arm,coresight-cpu-debug", "arm,primecell";
+                       reg = <0x0 0xfec10000 0x0 0x1000>;
+                       clock-names = "apb_pclk";
+                       cpu = <&cpu0>;
+               };
+
+               cpu1_debug: debug@fed10000 {
+                       compatible = "arm,coresight-cpu-debug", "arm,primecell";
+                       reg = <0x0 0xfed10000 0x0 0x1000>;
+                       clock-names = "apb_pclk";
+                       cpu = <&cpu1>;
+               };
+
+               cpu2_debug: debug@fee10000 {
+                       compatible = "arm,coresight-cpu-debug", "arm,primecell";
+                       reg = <0x0 0xfee10000 0x0 0x1000>;
+                       clock-names = "apb_pclk";
+                       cpu = <&cpu2>;
+               };
+
+               cpu3_debug: debug@fef10000 {
+                       compatible = "arm,coresight-cpu-debug", "arm,primecell";
+                       reg = <0x0 0xfef10000 0x0 0x1000>;
+                       clock-names = "apb_pclk";
+                       cpu = <&cpu3>;
+               };
+
                /* GDMA */
                fpd_dma_chan1: dma-controller@fd500000 {
                        status = "disabled";