net: renesas: rswitch: fix initial MPIC register setting

MPIC.PIS must be set per phy interface type.
MPIC.LSC must be set per speed.

Do that strictly per datasheet, instead of hardcoding MPIC.PIS to GMII.

Fixes: 3590918b5d07 ("net: ethernet: renesas: Add support for "Ethernet Switch"")
Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Reviewed-by: Michal Swiatkowski <michal.swiatkowski@linux.intel.com>
Link: https://patch.msgid.link/20241211053012.368914-1-nikita.yoush@cogentembedded.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

diff --git a/drivers/net/ethernet/renesas/rswitch.c b/drivers/net/ethernet/renesas/rswitch.c
index 6ec71478957396b2c0f604496e5feba6f2de6008..dbbbf024e7abc8657bf4090a9bf5a19cc90d9d70 100644 (file)
--- a/drivers/net/ethernet/renesas/rswitch.c
+++ b/drivers/net/ethernet/renesas/rswitch.c
@@ -1116,25 +1116,40 @@ static int rswitch_etha_wait_link_verification(struct rswitch_etha *etha)
 
 static void rswitch_rmac_setting(struct rswitch_etha *etha, const u8 *mac)
 {
-       u32 val;
+       u32 pis, lsc;
 
        rswitch_etha_write_mac_address(etha, mac);
 
+       switch (etha->phy_interface) {
+       case PHY_INTERFACE_MODE_SGMII:
+               pis = MPIC_PIS_GMII;
+               break;
+       case PHY_INTERFACE_MODE_USXGMII:
+       case PHY_INTERFACE_MODE_5GBASER:
+               pis = MPIC_PIS_XGMII;
+               break;
+       default:
+               pis = FIELD_GET(MPIC_PIS, ioread32(etha->addr + MPIC));
+               break;
+       }
+
        switch (etha->speed) {
        case 100:
-               val = MPIC_LSC_100M;
+               lsc = MPIC_LSC_100M;
                break;
        case 1000:
-               val = MPIC_LSC_1G;
+               lsc = MPIC_LSC_1G;
                break;
        case 2500:
-               val = MPIC_LSC_2_5G;
+               lsc = MPIC_LSC_2_5G;
                break;
        default:
-               return;
+               lsc = FIELD_GET(MPIC_LSC, ioread32(etha->addr + MPIC));
+               break;
        }
 
-       iowrite32(MPIC_PIS_GMII | val, etha->addr + MPIC);
+       rswitch_modify(etha->addr, MPIC, MPIC_PIS | MPIC_LSC,
+                      FIELD_PREP(MPIC_PIS, pis) | FIELD_PREP(MPIC_LSC, lsc));
 }
 
 static void rswitch_etha_enable_mii(struct rswitch_etha *etha)

diff --git a/drivers/net/ethernet/renesas/rswitch.h b/drivers/net/ethernet/renesas/rswitch.h
index 72e3ff596d3183fa6512516907d485937aee316c..e020800dcc570e1f622ee72d988398dce9fcd31a 100644 (file)
--- a/drivers/net/ethernet/renesas/rswitch.h
+++ b/drivers/net/ethernet/renesas/rswitch.h
@@ -724,13 +724,13 @@ enum rswitch_etha_mode {
 
 #define EAVCC_VEM_SC_TAG       (0x3 << 16)
 
-#define MPIC_PIS_MII           0x00
-#define MPIC_PIS_GMII          0x02
-#define MPIC_PIS_XGMII         0x04
-#define MPIC_LSC_SHIFT         3
-#define MPIC_LSC_100M          (1 << MPIC_LSC_SHIFT)
-#define MPIC_LSC_1G            (2 << MPIC_LSC_SHIFT)
-#define MPIC_LSC_2_5G          (3 << MPIC_LSC_SHIFT)
+#define MPIC_PIS               GENMASK(2, 0)
+#define MPIC_PIS_GMII          2
+#define MPIC_PIS_XGMII         4
+#define MPIC_LSC               GENMASK(5, 3)
+#define MPIC_LSC_100M          1
+#define MPIC_LSC_1G            2
+#define MPIC_LSC_2_5G          3
 
 #define MDIO_READ_C45          0x03
 #define MDIO_WRITE_C45         0x01