if (!(prot & IOMMU_WRITE) && (prot & IOMMU_READ))
                        pte |= ARM_LPAE_PTE_AP_RDONLY;
 
-               if (prot & IOMMU_CACHE)
+               if (prot & IOMMU_MMIO)
+                       pte |= (ARM_LPAE_MAIR_ATTR_IDX_DEV
+                               << ARM_LPAE_PTE_ATTRINDX_SHIFT);
+               else if (prot & IOMMU_CACHE)
                        pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
                                << ARM_LPAE_PTE_ATTRINDX_SHIFT);
        } else {
                        pte |= ARM_LPAE_PTE_HAP_READ;
                if (prot & IOMMU_WRITE)
                        pte |= ARM_LPAE_PTE_HAP_WRITE;
-               if (prot & IOMMU_CACHE)
+               if (prot & IOMMU_MMIO)
+                       pte |= ARM_LPAE_PTE_MEMATTR_DEV;
+               else if (prot & IOMMU_CACHE)
                        pte |= ARM_LPAE_PTE_MEMATTR_OIWB;
                else
                        pte |= ARM_LPAE_PTE_MEMATTR_NC;