#define E1000_DEV_ID_PCH_CMP_I219_V11          0x0D4D
 #define E1000_DEV_ID_PCH_CMP_I219_LM12         0x0D53
 #define E1000_DEV_ID_PCH_CMP_I219_V12          0x0D55
+#define E1000_DEV_ID_PCH_TGP_I219_LM13         0x15FB
+#define E1000_DEV_ID_PCH_TGP_I219_V13          0x15FC
+#define E1000_DEV_ID_PCH_TGP_I219_LM14         0x15F9
+#define E1000_DEV_ID_PCH_TGP_I219_V14          0x15FA
+#define E1000_DEV_ID_PCH_TGP_I219_LM15         0x15F4
 
 #define E1000_REVISION_4       4
 
        e1000_pch_lpt,
        e1000_pch_spt,
        e1000_pch_cnp,
+       e1000_pch_tgp,
 };
 
 enum e1000_media_type {
 
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
+       case e1000_pch_tgp:
                if (e1000_phy_is_accessible_pchlan(hw))
                        break;
 
                case e1000_pch_lpt:
                case e1000_pch_spt:
                case e1000_pch_cnp:
+               case e1000_pch_tgp:
                        /* In case the PHY needs to be in mdio slow mode,
                         * set slow mode and try to get the PHY id again.
                         */
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
+       case e1000_pch_tgp:
        case e1000_pchlan:
                /* check management mode */
                mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
+       case e1000_pch_tgp:
                rc = e1000_init_phy_params_pchlan(hw);
                break;
        default:
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
+       case e1000_pch_tgp:
                sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
                break;
        default:
        switch (hw->mac.type) {
        case e1000_pch_spt:
        case e1000_pch_cnp:
+       case e1000_pch_tgp:
                bank1_offset = nvm->flash_bank_size;
                act_offset = E1000_ICH_NVM_SIG_WORD;
 
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
+       case e1000_pch_tgp:
                word = NVM_COMPAT;
                valid_csum_mask = NVM_COMPAT_VALID_CSUM;
                break;
 
                adapter->cc.shift = shift;
                break;
        case e1000_pch_cnp:
+       case e1000_pch_tgp:
                if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
                        /* Stable 24MHz frequency */
                        incperiod = INCPERIOD_24MHZ;
        case e1000_pch_lpt:
        case e1000_pch_spt:
        case e1000_pch_cnp:
+               /* fall-through */
+       case e1000_pch_tgp:
                fc->refresh_time = 0xFFFF;
                fc->pause_time = 0xFFFF;
 
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_cnp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_cnp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_cnp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_cnp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_cnp },
 
        { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
 };