writel(cmd_base.ul, privdata->mmio + AMD_C2P_MSG0);
 }
 
+static void amd_sfh_clear_intr_v2(struct amd_mp2_dev *privdata)
+{
+       if (readl(privdata->mmio + AMD_P2C_MSG(4))) {
+               writel(0, privdata->mmio + AMD_P2C_MSG(4));
+               writel(0xf, privdata->mmio + AMD_P2C_MSG(5));
+       }
+}
+
+static void amd_sfh_clear_intr(struct amd_mp2_dev *privdata)
+{
+       if (privdata->mp2_ops->clear_intr)
+               privdata->mp2_ops->clear_intr(privdata);
+}
+
 void amd_start_sensor(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info)
 {
        union sfh_cmd_param cmd_param;
        struct amd_mp2_dev *mp2 = privdata;
        amd_sfh_hid_client_deinit(privdata);
        mp2->mp2_ops->stop_all(mp2);
+       amd_sfh_clear_intr(mp2);
 }
 
 static const struct amd_mp2_ops amd_sfh_ops_v2 = {
        .stop = amd_stop_sensor_v2,
        .stop_all = amd_stop_all_sensor_v2,
        .response = amd_sfh_wait_response_v2,
+       .clear_intr = amd_sfh_clear_intr_v2,
 };
 
 static const struct amd_mp2_ops amd_sfh_ops = {
        mp2_select_ops(privdata);
 
        rc = amd_sfh_hid_client_init(privdata);
-       if (rc)
+       if (rc) {
+               amd_sfh_clear_intr(privdata);
+               dev_err(&pdev->dev, "amd_sfh_hid_client_init failed\n");
                return rc;
+       }
+
+       amd_sfh_clear_intr(privdata);
 
        return devm_add_action_or_reset(&pdev->dev, amd_mp2_pci_remove, privdata);
 }
        }
 
        schedule_delayed_work(&cl_data->work_buffer, msecs_to_jiffies(AMD_SFH_IDLE_LOOP));
+       amd_sfh_clear_intr(mp2);
 
        return 0;
 }
        }
 
        cancel_delayed_work_sync(&cl_data->work_buffer);
+       amd_sfh_clear_intr(mp2);
 
        return 0;
 }