For details about the current modifications, please see README-WIP
+* Add support for redundand environment, so the previous settins
+ don't get lost in case of a power failure right during a "saveenv"
+ command.
+ Major restructuring and cleanup of the environment handling.
+
+* Patch by Stefan Roese, 18 Jul 2002:
+ Removed board init.S from esd AR405, CANBT, CPCIISER4, OCRTC
+ targets -> no (E)ABI violation anymore with r31 usage (setup
+ moved to config files).
+
* Patch by David Müller, 17 Sep 2002:
fix SMDK2410 configuration.
add (compile time selectable) support for LV400 and LV800 flash.
wrong before the contents has been restored from a copy in
RAM, your target system will be dead.
+ - CFG_ENV_ADDR_REDUND
+ CFG_ENV_SIZE_REDUND
+
+ These settings describe a second storage area used to hold
+ a redundand copy of the environment data, so that there is
+ a valid backup copy in case there is a power failur during
+ a "saveenv" operation.
BE CAREFUL! Any changes to the flash layout, and some changes to the
source code will make it necessary to adapt <board>/ppcboot.lds*
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
-SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
+++ /dev/null
-//------------------------------------------------------------------------------+
-//
-// This source code has been made available to you by IBM on an AS-IS
-// basis. Anyone receiving this source is licensed under IBM
-// copyrights to use it in any way he or she deems fit, including
-// copying it, modifying it, compiling it, and redistributing it either
-// with or without modifications. No license under IBM patents or
-// patent applications is to be implied by the copyright license.
-//
-// Any user of this software should understand that IBM cannot provide
-// technical support for this software and will not be responsible for
-// any consequences resulting from the use of this software.
-//
-// Any person who transfers this source code or any derivative work
-// must include the IBM copyright notice, this paragraph, and the
-// preceding two paragraphs in the transferred software.
-//
-// COPYRIGHT I B M CORPORATION 1995
-// LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
-//-------------------------------------------------------------------------------
-
-//-----------------------------------------------------------------------------
-// Function: ext_bus_cntlr_init
-// Description: Initializes the External Bus Controller for the external
-// peripherals. IMPORTANT: For pass1 this code must run from
-// cache since you can not reliably change a peripheral banks
-// timing register (pbxap) while running code from that bank.
-// For ex., since we are running from ROM on bank 0, we can NOT
-// execute the code that modifies bank 0 timings from ROM, so
-// we run it from cache.
-// Bank 0 - Flash bank 0
-// Bank 1 - CAN0, CAN1, CAN2, CAN3
-// Bank 2 - Expansion Bus
-// Bank 3 - 16552
-// Bank 4 - FPGA internal (ADC, DAC, etc.)
-// Bank 5 - Flash bank 1 (dummy)
-//-----------------------------------------------------------------------------
-#include <config.h>
-#include <ppc4xx.h>
-
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- mflr r4 // save link register
- bl ..getAddr
-..getAddr:
- mflr r3 // get address of ..getAddr
- mtlr r4 // restore link register
- addi r4,0,14 // set ctr to 10; used to prefetch
- mtctr r4 // 10 cache lines to fit this function
- // in cache (gives us 8x10=80 instrctns)
-..ebcloop:
- icbt r0,r3 // prefetch cache line for addr in r3
- addi r3,r3,32 // move to next cache line
- bdnz ..ebcloop // continue for 10 cache lines
-
- //-------------------------------------------------------------------
- // Delay to ensure all accesses to ROM are complete before changing
- // bank 0 timings. 200usec should be enough.
- // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- //-------------------------------------------------------------------
- addis r3,0,0x0
- ori r3,r3,0xA000 // ensure 200usec have passed since reset
- mtctr r3
-..spinlp:
- bdnz ..spinlp // spin loop
-
- //-----------------------------------------------------------------------
- // Memory Bank 0 (Flash Bank 0) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb0ap
- mtdcr ebccfga,r4
- addis r4,0,0x9201
- ori r4,r4,0x5480
- mtdcr ebccfgd,r4
-
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
- addis r4,0,0xFFC5 // BAS=0xFFC,BS=0x2(4MB),BU=0x3(R/W),
- ori r4,r4,0xA000 // BW=0x1(16 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 5 (Flash Bank 1) initialization (dummy for flash_init only!!!)
- //-----------------------------------------------------------------------
- addi r4,0,pb5ap
- mtdcr ebccfga,r4
- addis r4,0,0x9201
- ori r4,r4,0x5480
- mtdcr ebccfgd,r4
-
- addi r4,0,pb5cr
- mtdcr ebccfga,r4
- addis r4,0,0xFF85 // BAS=0xFF8,BS=0x2(4MB),BU=0x3(R/W),
- ori r4,r4,0xA000 // BW=0x1(16 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 1 (CAN0, 1, 2, 3) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb1ap
- mtdcr ebccfga,r4
- addis r4,0,0x0100
- ori r4,r4,0x0380 // enable Ready, BEM=0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb1cr
- mtdcr ebccfga,r4
- addis r4,0,0xF001 // BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0x8000 // BW=0x0(8 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 2 (Expension bus) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb2ap
- mtdcr ebccfga,r4
- addis r4,0,0x0100
- ori r4,r4,0x0280 // disable Ready, BEM=0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb2cr
- mtdcr ebccfga,r4
- addis r4,0,0xF011 // BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0x8000 // BW=0x0(8 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 3 (16552) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb3ap
- mtdcr ebccfga,r4
- addis r4,0,0x0100
- ori r4,r4,0x0380 // enable Ready, BEM=0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb3cr
- mtdcr ebccfga,r4
- addis r4,0,0xF021 // BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0x8000 // BW=0x0(8 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 4 (FPGA internal - DAC, ADC, etc) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb4ap
- mtdcr ebccfga,r4
- addis r4,0,0x0100
- ori r4,r4,0x5380 // enable Ready, BEM=0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb4cr
- mtdcr ebccfga,r4
- addis r4,0,0xF031 // BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0xc000 // BW=0x10(32 bits)
- mtdcr ebccfgd,r4
-
- nop // pass2 DCR errata #8
- blr
-
-//-----------------------------------------------------------------------------
-// Function: sdram_init
-// Description: Configures SDRAM memory banks.
-// Auto Memory Configuration option reads the SDRAM EEPROM
-// via the IIC bus and then configures the SDRAM memory
-// banks appropriately. If Auto Memory Configuration is
-// is not used, it is assumed that a 32MB 12x8(2) non-ECC DIMM is
-// plugged, ie. the DIMM that shipped wih the Eval board.
-//-----------------------------------------------------------------------------
- .globl sdram_init
-
-sdram_init:
-
- mflr r31
-
- //-------------------------------------------------------------------
- // Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4)
- //-------------------------------------------------------------------
- addi r4,0,mem_mb0cf
- mtdcr memcfga,r4
- addis r4,0,0x0004
- ori r4,r4,0x6001
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
- // To set the appropriate timings, we need to know the SDRAM speed.
- // We can use the PLB speed since the SDRAM speed is the same as
- // the PLB speed. The PLB speed is the FBK divider times the
- // 405GP reference clock, which on the Walnut board is 33Mhz.
- // Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is
- // 100Mhz; if FBK is 3, SDRAM is 133Mhz.
- // NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and
- // maybe 133Mhz.
- //-------------------------------------------------------------------
- mfdcr r5,strap // determine FBK divider
- // via STRAP reg to calc PLB speed.
- // SDRAM speed is the same as the PLB
- // speed.
- rlwinm r4,r5,4,0x3 // get FBK divide bits
-
-..chk_66:
- cmpi %cr0,0,r4,0x1
- bne ..chk_100
- addis r6,0,0x0085 // SDTR1 value for 66Mhz
- ori r6,r6,0x4005
- addis r7,0,0x03F8 // RTR value for 66Mhz
- b ..sdram_ok
-..chk_100:
- cmpi %cr0,0,r4,0x2
- bne ..chk_133
- addis r6,0,0x0086 // SDTR1 value for 100Mhz
- ori r6,r6,0x400D
- addis r7,0,0x05F0 // RTR value for 100Mhz
- b ..sdram_ok
-..chk_133:
- addis r6,0,0x0107 // SDTR1 value for 133Mhz
- ori r6,r6,0x4015
- addis r7,0,0x07F0 // RTR value for 133Mhz
-
-..sdram_ok:
- //-------------------------------------------------------------------
- // Set SDTR1
- //-------------------------------------------------------------------
- addi r4,0,mem_sdtr1
- mtdcr memcfga,r4
- mtdcr memcfgd,r6
-
- //-------------------------------------------------------------------
- // Set RTR
- //-------------------------------------------------------------------
- addi r4,0,mem_rtr
- mtdcr memcfga,r4
- mtdcr memcfgd,r7
-
- //-------------------------------------------------------------------
- // Delay to ensure 200usec have elapsed since reset. Assume worst
- // case that the core is running 200Mhz:
- // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- //-------------------------------------------------------------------
- addis r3,0,0x0000
- ori r3,r3,0xA000 // ensure 200usec have passed since reset
- mtctr r3
-..spinlp2:
- bdnz ..spinlp2 // spin loop
-
- //-------------------------------------------------------------------
- // Set memory controller options reg, MCOPT1.
- // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
- // read/prefetch.
- //-------------------------------------------------------------------
- addi r4,0,mem_mcopt1
- mtdcr memcfga,r4
- addis r4,0,0x8080 // set DC_EN=1
- ori r4,r4,0x0000
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Delay to ensure 10msec have elapsed since reset. This is
- // required for the MPC952 to stabalize. Assume worst
- // case that the core is running 200Mhz:
- // 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles
- // This delay should occur before accessing SDRAM.
- //-------------------------------------------------------------------
- addis r3,0,0x001E
- ori r3,r3,0x8480 // ensure 10msec have passed since reset
- mtctr r3
-..spinlp3:
- bdnz ..spinlp3 // spin loop
-
- mtlr r31 // restore lr
- blr
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- board/esd/ar405/init.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
-SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
+++ /dev/null
-//------------------------------------------------------------------------------+
-//
-// This source code has been made available to you by IBM on an AS-IS
-// basis. Anyone receiving this source is licensed under IBM
-// copyrights to use it in any way he or she deems fit, including
-// copying it, modifying it, compiling it, and redistributing it either
-// with or without modifications. No license under IBM patents or
-// patent applications is to be implied by the copyright license.
-//
-// Any user of this software should understand that IBM cannot provide
-// technical support for this software and will not be responsible for
-// any consequences resulting from the use of this software.
-//
-// Any person who transfers this source code or any derivative work
-// must include the IBM copyright notice, this paragraph, and the
-// preceding two paragraphs in the transferred software.
-//
-// COPYRIGHT I B M CORPORATION 1995
-// LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
-//-------------------------------------------------------------------------------
-
-//-----------------------------------------------------------------------------
-// Function: ext_bus_cntlr_init
-// Description: Initializes the External Bus Controller for the external
-// peripherals. IMPORTANT: For pass1 this code must run from
-// cache since you can not reliably change a peripheral banks
-// timing register (pbxap) while running code from that bank.
-// For ex., since we are running from ROM on bank 0, we can NOT
-// execute the code that modifies bank 0 timings from ROM, so
-// we run it from cache.
-// Bank 0 - Flash bank 0
-// Bank 1 - Flash bank 1
-// Bank 2 - CAN0, CAN1, CAN2, Codeswitch (0x000,0x100,0x200,0x400)
-// Bank 3 - IDE (CompactFlash)
-// Bank 4 - Quart
-// Bank 5 - not used
-// Bank 6 - not used
-// Bank 7 - not used
-//-----------------------------------------------------------------------------
-#include <config.h>
-#include <ppc4xx.h>
-
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- mflr r4 // save link register
- bl ..getAddr
-..getAddr:
- mflr r3 // get address of ..getAddr
- mtlr r4 // restore link register
- addi r4,0,14 // set ctr to 10; used to prefetch
- mtctr r4 // 10 cache lines to fit this function
- // in cache (gives us 8x10=80 instrctns)
-..ebcloop:
- icbt r0,r3 // prefetch cache line for addr in r3
- addi r3,r3,32 // move to next cache line
- bdnz ..ebcloop // continue for 10 cache lines
-
- //-------------------------------------------------------------------
- // Delay to ensure all accesses to ROM are complete before changing
- // bank 0 timings. 200usec should be enough.
- // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- //-------------------------------------------------------------------
- addis r3,0,0x0
- ori r3,r3,0xA000 // ensure 200usec have passed since reset
- mtctr r3
-..spinlp:
- bdnz ..spinlp // spin loop
-
- //-----------------------------------------------------------------------
- // Memory Bank 0 (Flash Bank 0) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb0ap
- mtdcr ebccfga,r4
- addis r4,0,0x9201
- ori r4,r4,0x5480
- mtdcr ebccfgd,r4
-
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
- addis r4,0,0xFFC5 // BAS=0xFFC,BS=0x2(4MB),BU=0x3(R/W),
- ori r4,r4,0xA000 // BW=0x1(16 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 1 (CAN/USB Bank 1) initialization (ADDR=0xf0000000)
- //-----------------------------------------------------------------------
- addi r4,0,pb1ap
- mtdcr ebccfga,r4
- addis r4,0,0x0100
- ori r4,r4,0x53c0 // enable Ready, BEM=1
- mtdcr ebccfgd,r4
-
- addi r4,0,pb1cr
- mtdcr ebccfga,r4
- addis r4,0,0xF001 // BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0x8000 // BW=0x0(8 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 2 (misc_io, LEDs) initialization (ADDR=0xf0100000)
- //-----------------------------------------------------------------------
- addi r4,0,pb2ap
- mtdcr ebccfga,r4
- addis r4,0,0x0000
- ori r4,r4,0x04c0 // disable Ready, BEM=1
- mtdcr ebccfgd,r4
-
- addi r4,0,pb2cr
- mtdcr ebccfga,r4
- addis r4,0,0xF011 // BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0x8000 // BW=0x0(8 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 3 (can_features) initialization (ADDR=0xf0200000)
- //-----------------------------------------------------------------------
- addi r4,0,pb3ap
- mtdcr ebccfga,r4
-// addis r4,0,0x0100
-// ori r4,r4,0x04c0 // disable Ready, BEM=1
- addis r4,0,0x8000
- ori r4,r4,0x0040 // disable Ready, BEM=1
- mtdcr ebccfgd,r4
-
- addi r4,0,pb3cr
- mtdcr ebccfga,r4
- addis r4,0,0xF021 // BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),
-// ori r4,r4,0xA000 // BW=0x1(16 bits)
- ori r4,r4,0xC000 // BW=0x1(32 bits)
- mtdcr ebccfgd,r4
-
- nop // pass2 DCR errata #8
- blr
-
-//-----------------------------------------------------------------------------
-// Function: sdram_init
-// Description: Configures SDRAM memory banks.
-// Auto Memory Configuration option reads the SDRAM EEPROM
-// via the IIC bus and then configures the SDRAM memory
-// banks appropriately. If Auto Memory Configuration is
-// is not used, it is assumed that a 32MB 12x8(2) non-ECC DIMM is
-// plugged, ie. the DIMM that shipped wih the Eval board.
-//-----------------------------------------------------------------------------
- .globl sdram_init
-
-sdram_init:
-
- mflr r31
-
- //-------------------------------------------------------------------
- // Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4)
- //-------------------------------------------------------------------
- addi r4,0,mem_mb0cf
- mtdcr memcfga,r4
- addis r4,0,0x0004
- ori r4,r4,0x6001
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
- // To set the appropriate timings, we need to know the SDRAM speed.
- // We can use the PLB speed since the SDRAM speed is the same as
- // the PLB speed. The PLB speed is the FBK divider times the
- // 405GP reference clock, which on the Walnut board is 33Mhz.
- // Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is
- // 100Mhz; if FBK is 3, SDRAM is 133Mhz.
- // NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and
- // maybe 133Mhz.
- //-------------------------------------------------------------------
- mfdcr r5,strap // determine FBK divider
- // via STRAP reg to calc PLB speed.
- // SDRAM speed is the same as the PLB
- // speed.
- rlwinm r4,r5,4,0x3 // get FBK divide bits
-
-..chk_66:
- cmpi %cr0,0,r4,0x1
- bne ..chk_100
- addis r6,0,0x0085 // SDTR1 value for 66Mhz
- ori r6,r6,0x4005
- addis r7,0,0x03F8 // RTR value for 66Mhz
- b ..sdram_ok
-..chk_100:
- cmpi %cr0,0,r4,0x2
- bne ..chk_133
- addis r6,0,0x0086 // SDTR1 value for 100Mhz
- ori r6,r6,0x400D
- addis r7,0,0x05F0 // RTR value for 100Mhz
- b ..sdram_ok
-..chk_133:
- addis r6,0,0x0107 // SDTR1 value for 133Mhz
- ori r6,r6,0x4015
- addis r7,0,0x07F0 // RTR value for 133Mhz
-
-..sdram_ok:
- //-------------------------------------------------------------------
- // Set SDTR1
- //-------------------------------------------------------------------
- addi r4,0,mem_sdtr1
- mtdcr memcfga,r4
- mtdcr memcfgd,r6
-
- //-------------------------------------------------------------------
- // Set RTR
- //-------------------------------------------------------------------
- addi r4,0,mem_rtr
- mtdcr memcfga,r4
- mtdcr memcfgd,r7
-
- //-------------------------------------------------------------------
- // Delay to ensure 200usec have elapsed since reset. Assume worst
- // case that the core is running 200Mhz:
- // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- //-------------------------------------------------------------------
- addis r3,0,0x0000
- ori r3,r3,0xA000 // ensure 200usec have passed since reset
- mtctr r3
-..spinlp2:
- bdnz ..spinlp2 // spin loop
-
- //-------------------------------------------------------------------
- // Set memory controller options reg, MCOPT1.
- // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
- // read/prefetch.
- //-------------------------------------------------------------------
- addi r4,0,mem_mcopt1
- mtdcr memcfga,r4
- addis r4,0,0x8080 // set DC_EN=1
- ori r4,r4,0x0000
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Delay to ensure 10msec have elapsed since reset. This is
- // required for the MPC952 to stabalize. Assume worst
- // case that the core is running 200Mhz:
- // 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles
- // This delay should occur before accessing SDRAM.
- //-------------------------------------------------------------------
- addis r3,0,0x001E
- ori r3,r3,0x8480 // ensure 10msec have passed since reset
- mtctr r3
-..spinlp3:
- bdnz ..spinlp3 // spin loop
-
- mtlr r31 // restore lr
- blr
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- board/esd/canbt/init.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
-SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
+++ /dev/null
-//------------------------------------------------------------------------------+
-//
-// This source code has been made available to you by IBM on an AS-IS
-// basis. Anyone receiving this source is licensed under IBM
-// copyrights to use it in any way he or she deems fit, including
-// copying it, modifying it, compiling it, and redistributing it either
-// with or without modifications. No license under IBM patents or
-// patent applications is to be implied by the copyright license.
-//
-// Any user of this software should understand that IBM cannot provide
-// technical support for this software and will not be responsible for
-// any consequences resulting from the use of this software.
-//
-// Any person who transfers this source code or any derivative work
-// must include the IBM copyright notice, this paragraph, and the
-// preceding two paragraphs in the transferred software.
-//
-// COPYRIGHT I B M CORPORATION 1995
-// LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
-//-------------------------------------------------------------------------------
-
-//-----------------------------------------------------------------------------
-// Function: ext_bus_cntlr_init
-// Description: Initializes the External Bus Controller for the external
-// peripherals. IMPORTANT: For pass1 this code must run from
-// cache since you can not reliably change a peripheral banks
-// timing register (pbxap) while running code from that bank.
-// For ex., since we are running from ROM on bank 0, we can NOT
-// execute the code that modifies bank 0 timings from ROM, so
-// we run it from cache.
-// Bank 0 - Flash bank 0
-// Bank 1 - Flash bank 1
-// Bank 2 - CAN0, CAN1, CAN2, Codeswitch (0x000,0x100,0x200,0x400)
-// Bank 3 - IDE (CompactFlash)
-// Bank 4 - Quart
-// Bank 5 - not used
-// Bank 6 - not used
-// Bank 7 - not used
-//-----------------------------------------------------------------------------
-#include <config.h>
-#include <ppc4xx.h>
-
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- mflr r4 // save link register
- bl ..getAddr
-..getAddr:
- mflr r3 // get address of ..getAddr
- mtlr r4 // restore link register
- addi r4,0,14 // set ctr to 10; used to prefetch
- mtctr r4 // 10 cache lines to fit this function
- // in cache (gives us 8x10=80 instrctns)
-..ebcloop:
- icbt r0,r3 // prefetch cache line for addr in r3
- addi r3,r3,32 // move to next cache line
- bdnz ..ebcloop // continue for 10 cache lines
-
- //-------------------------------------------------------------------
- // Delay to ensure all accesses to ROM are complete before changing
- // bank 0 timings. 200usec should be enough.
- // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- //-------------------------------------------------------------------
- addis r3,0,0x0
- ori r3,r3,0xA000 // ensure 200usec have passed since reset
- mtctr r3
-..spinlp:
- bdnz ..spinlp // spin loop
-
- //-----------------------------------------------------------------------
- // Memory Bank 0 (Flash Bank 0) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb0ap
- mtdcr ebccfga,r4
- addis r4,0,0x9201
- ori r4,r4,0x5480
- mtdcr ebccfgd,r4
-
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
- addis r4,0,0xFFC5 // BAS=0xFFC,BS=0x2(4MB),BU=0x3(R/W),
- ori r4,r4,0xA000 // BW=0x1(16 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 1 (UART 8bit) initialization (ADDR=0xf0000000)
- //-----------------------------------------------------------------------
- addi r4,0,pb1ap
- mtdcr ebccfga,r4
- addis r4,0,0x0100 // TWT=2
- ori r4,r4,0x0480 // TH=2, disable Ready, BEM=0, SOR=1
- mtdcr ebccfgd,r4
-
- addi r4,0,pb1cr
- mtdcr ebccfga,r4
- addis r4,0,0xF001 // BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0x8000 // BW=0x0(8 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 2 (UART 32bit) initialization (ADDR=0xf0100000)
- //-----------------------------------------------------------------------
- addi r4,0,pb2ap
- mtdcr ebccfga,r4
- addis r4,0,0x0000
- ori r4,r4,0x04c0 // disable Ready, BEM=1
- mtdcr ebccfgd,r4
-
- addi r4,0,pb2cr
- mtdcr ebccfga,r4
- addis r4,0,0xF011 // BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0xC000 // BW=0x2(32 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 3 (FPGA Reset) initialization (ADDR=0xf0200000)
- //-----------------------------------------------------------------------
- addi r4,0,pb3ap
- mtdcr ebccfga,r4
- addis r4,0,0x0100
- ori r4,r4,0x04c0 // disable Ready, BEM=1
- mtdcr ebccfgd,r4
-
- addi r4,0,pb3cr
- mtdcr ebccfga,r4
- addis r4,0,0xF021 // BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0xA000 // BW=0x1(16 bits)
- mtdcr ebccfgd,r4
-
- nop // pass2 DCR errata #8
- blr
-
-//-----------------------------------------------------------------------------
-// Function: sdram_init
-// Description: Configures SDRAM memory banks.
-// Auto Memory Configuration option reads the SDRAM EEPROM
-// via the IIC bus and then configures the SDRAM memory
-// banks appropriately. If Auto Memory Configuration is
-// is not used, it is assumed that a 32MB 12x8(2) non-ECC DIMM is
-// plugged, ie. the DIMM that shipped wih the Eval board.
-//-----------------------------------------------------------------------------
- .globl sdram_init
-
-sdram_init:
-
- mflr r31
-
- //-------------------------------------------------------------------
- // Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4)
- //-------------------------------------------------------------------
- addi r4,0,mem_mb0cf
- mtdcr memcfga,r4
- addis r4,0,0x0004
- ori r4,r4,0x6001
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
- // To set the appropriate timings, we need to know the SDRAM speed.
- // We can use the PLB speed since the SDRAM speed is the same as
- // the PLB speed. The PLB speed is the FBK divider times the
- // 405GP reference clock, which on the Walnut board is 33Mhz.
- // Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is
- // 100Mhz; if FBK is 3, SDRAM is 133Mhz.
- // NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and
- // maybe 133Mhz.
- //-------------------------------------------------------------------
- mfdcr r5,strap // determine FBK divider
- // via STRAP reg to calc PLB speed.
- // SDRAM speed is the same as the PLB
- // speed.
- rlwinm r4,r5,4,0x3 // get FBK divide bits
-
-..chk_66:
- cmpi %cr0,0,r4,0x1
- bne ..chk_100
- addis r6,0,0x0085 // SDTR1 value for 66Mhz
- ori r6,r6,0x4005
- addis r7,0,0x03F8 // RTR value for 66Mhz
- b ..sdram_ok
-..chk_100:
- cmpi %cr0,0,r4,0x2
- bne ..chk_133
- addis r6,0,0x0086 // SDTR1 value for 100Mhz
- ori r6,r6,0x400D
- addis r7,0,0x05F0 // RTR value for 100Mhz
- b ..sdram_ok
-..chk_133:
- addis r6,0,0x0107 // SDTR1 value for 133Mhz
- ori r6,r6,0x4015
- addis r7,0,0x07F0 // RTR value for 133Mhz
-
-..sdram_ok:
- //-------------------------------------------------------------------
- // Set SDTR1
- //-------------------------------------------------------------------
- addi r4,0,mem_sdtr1
- mtdcr memcfga,r4
- mtdcr memcfgd,r6
-
- //-------------------------------------------------------------------
- // Set RTR
- //-------------------------------------------------------------------
- addi r4,0,mem_rtr
- mtdcr memcfga,r4
- mtdcr memcfgd,r7
-
- //-------------------------------------------------------------------
- // Delay to ensure 200usec have elapsed since reset. Assume worst
- // case that the core is running 200Mhz:
- // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- //-------------------------------------------------------------------
- addis r3,0,0x0000
- ori r3,r3,0xA000 // ensure 200usec have passed since reset
- mtctr r3
-..spinlp2:
- bdnz ..spinlp2 // spin loop
-
- //-------------------------------------------------------------------
- // Set memory controller options reg, MCOPT1.
- // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
- // read/prefetch.
- //-------------------------------------------------------------------
- addi r4,0,mem_mcopt1
- mtdcr memcfga,r4
- addis r4,0,0x8080 // set DC_EN=1
- ori r4,r4,0x0000
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Delay to ensure 10msec have elapsed since reset. This is
- // required for the MPC952 to stabalize. Assume worst
- // case that the core is running 200Mhz:
- // 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles
- // This delay should occur before accessing SDRAM.
- //-------------------------------------------------------------------
- addis r3,0,0x001E
- ori r3,r3,0x8480 // ensure 10msec have passed since reset
- mtctr r3
-..spinlp3:
- bdnz ..spinlp3 // spin loop
-
- mtlr r31 // restore lr
- blr
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- board/esd/cpciiser4/init.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
-SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
+++ /dev/null
-//------------------------------------------------------------------------------+
-//
-// This source code has been made available to you by IBM on an AS-IS
-// basis. Anyone receiving this source is licensed under IBM
-// copyrights to use it in any way he or she deems fit, including
-// copying it, modifying it, compiling it, and redistributing it either
-// with or without modifications. No license under IBM patents or
-// patent applications is to be implied by the copyright license.
-//
-// Any user of this software should understand that IBM cannot provide
-// technical support for this software and will not be responsible for
-// any consequences resulting from the use of this software.
-//
-// Any person who transfers this source code or any derivative work
-// must include the IBM copyright notice, this paragraph, and the
-// preceding two paragraphs in the transferred software.
-//
-// COPYRIGHT I B M CORPORATION 1995
-// LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
-//-------------------------------------------------------------------------------
-
-//-----------------------------------------------------------------------------
-// Function: ext_bus_cntlr_init
-// Description: Initializes the External Bus Controller for the external
-// peripherals. IMPORTANT: For pass1 this code must run from
-// cache since you can not reliably change a peripheral banks
-// timing register (pbxap) while running code from that bank.
-// For ex., since we are running from ROM on bank 0, we can NOT
-// execute the code that modifies bank 0 timings from ROM, so
-// we run it from cache.
-// Bank 0 - Flash bank 0
-// Bank 1 - Flash bank 1
-// Bank 2 - PLD - 1
-// Bank 3 - PLD - 2
-// Bank 4 - Spartan2 - 1
-// Bank 5 - Spartan2 - 2
-// Bank 6 - Virtex - 1
-// Bank 7 - Virtex - 2
-//-----------------------------------------------------------------------------
-#include <config.h>
-#include <ppc4xx.h>
-
-#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
-
-#define MAGIC0 0x00000000
-#define MAGIC1 0x11111111
-#define MAGIC2 0x22222222
-#define MAGIC3 0x33333333
-#define MAGIC4 0x44444444
-
-#define ADDR_ZERO 0x00000000
-#define ADDR_400 0x00000400
-#define ADDR_08MB 0x00800000
-#define ADDR_16MB 0x01000000
-#define ADDR_32MB 0x02000000
-#define ADDR_64MB 0x04000000
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- mflr r4 // save link register
- bl ..getAddr
-..getAddr:
- mflr r3 // get address of ..getAddr
- mtlr r4 // restore link register
- addi r4,0,18 // set ctr to 10; used to prefetch
- mtctr r4 // 10 cache lines to fit this function
- // in cache (gives us 8x10=80 instrctns)
-..ebcloop:
- icbt r0,r3 // prefetch cache line for addr in r3
- addi r3,r3,32 // move to next cache line
- bdnz ..ebcloop // continue for 10 cache lines
-
- //-------------------------------------------------------------------
- // Delay to ensure all accesses to ROM are complete before changing
- // bank 0 timings. 200usec should be enough.
- // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- //-------------------------------------------------------------------
- addis r3,0,0x0
- ori r3,r3,0xA000 // ensure 200usec have passed since reset
- mtctr r3
-..spinlp:
- bdnz ..spinlp // spin loop
-
- //-----------------------------------------------------------------------
- // Memory Bank 0 (Flash Bank 0) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb0ap
- mtdcr ebccfga,r4
- addis r4,0,0x9201
- ori r4,r4,0x5480 // disable Ready
- mtdcr ebccfgd,r4
-
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
- addis r4,0,0xFFC5 // BAS=0xFFC,BS=0x2(4MB),BU=0x3(R/W),
- ori r4,r4,0xA000 // BW=0x1(16 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 1 (Flash Bank 1) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb1ap
- mtdcr ebccfga,r4
- addis r4,0,0x9201
- ori r4,r4,0x5480 // disable Ready
- mtdcr ebccfgd,r4
-
- addi r4,0,pb1cr
- mtdcr ebccfga,r4
- addis r4,0,0xFF85 // BAS=0xFF8,BS=0x2(4MB),BU=0x3(R/W),
- ori r4,r4,0xA000 // BW=0x1(16 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 2 (PLD - FPGA-boot) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb2ap
- mtdcr ebccfga,r4
- addis r4,0,0x0201 // BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1
- ori r4,r4,0x5480 // WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb2cr
- mtdcr ebccfga,r4
- addis r4,0,0xF001 // BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0x8000 // BW=0x0(8 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 3 (PLD - OSL) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb3ap
- mtdcr ebccfga,r4
- addis r4,0,0x0201 // BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1
- ori r4,r4,0x5480 // WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb3cr
- mtdcr ebccfga,r4
- addis r4,0,0xF011 // BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),
- ori r4,r4,0x8000 // BW=0x0(8 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 4 (Spartan2 1) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb4ap
- mtdcr ebccfga,r4
- addis r4,0,0x0201 // BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1
- ori r4,r4,0x5580 // WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb4cr
- mtdcr ebccfga,r4
- addis r4,0,0xF209 // BAS=0xF20,BS=0x4(16MB),BU=0x3(R/W),
- ori r4,r4,0xc000 // BW=0x2(32 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 5 (Spartan2 2) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb5ap
- mtdcr ebccfga,r4
- addis r4,0,0x0201 // BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1
- ori r4,r4,0x5580 // WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb5cr
- mtdcr ebccfga,r4
- addis r4,0,0xF309 // BAS=0xF30,BS=0x4(16MB),BU=0x3(R/W),
- ori r4,r4,0xc000 // BW=0x2(32 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 6 (Virtex 1) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb6ap
- mtdcr ebccfga,r4
- addis r4,0,0x0201 // BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1
- ori r4,r4,0x5580 // WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb6cr
- mtdcr ebccfga,r4
- addis r4,0,0xF409 // BAS=0xF40,BS=0x4(16MB),BU=0x3(R/W),
- ori r4,r4,0xa000 // BW=0x1(16 bits)
- mtdcr ebccfgd,r4
-
- //-----------------------------------------------------------------------
- // Memory Bank 7 (Virtex 2) initialization
- //-----------------------------------------------------------------------
- addi r4,0,pb7ap
- mtdcr ebccfga,r4
- addis r4,0,0x0201 // BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1
- ori r4,r4,0x5580 // WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0
- mtdcr ebccfgd,r4
-
- addi r4,0,pb7cr
- mtdcr ebccfga,r4
- addis r4,0,0xF509 // BAS=0xF50,BS=0x4(1MB),BU=0x3(R/W),
- ori r4,r4,0xa000 // BW=0x1(16 bits)
- mtdcr ebccfgd,r4
-
- nop // pass2 DCR errata #8
- blr
-
-//-----------------------------------------------------------------------------
-// Function: sdram_init
-// Description: Configures SDRAM memory banks.
-// Auto Memory Configuration option reads the SDRAM EEPROM
-// via the IIC bus and then configures the SDRAM memory
-// banks appropriately. If Auto Memory Configuration is
-// is not used, it is assumed that a 32MB 12x8(2) non-ECC DIMM is
-// plugged, ie. the DIMM that shipped wih the Eval board.
-//-----------------------------------------------------------------------------
- .globl sdram_init
-
-sdram_init:
-
- mflr r31
-
- //-------------------------------------------------------------------
- // Set MB0CF for bank 0. (0-64MB) Address Mode 3 since 13x9(4)
- //-------------------------------------------------------------------
- addi r4,0,mem_mb0cf
- mtdcr memcfga,r4
- addis r4,0,0x0008
- ori r4,r4,0x4001
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
- // To set the appropriate timings, we need to know the SDRAM speed.
- // We can use the PLB speed since the SDRAM speed is the same as
- // the PLB speed. The PLB speed is the FBK divider times the
- // 405GP reference clock, which on the Walnut board is 33Mhz.
- // Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is
- // 100Mhz; if FBK is 3, SDRAM is 133Mhz.
- // NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and
- // maybe 133Mhz.
- //-------------------------------------------------------------------
- mfdcr r5,strap // determine FBK divider
- // via STRAP reg to calc PLB speed.
- // SDRAM speed is the same as the PLB
- // speed.
- rlwinm r4,r5,4,0x3 // get FBK divide bits
-
-..chk_66:
- cmpi %cr0,0,r4,0x1
- bne ..chk_100
- addis r6,0,0x0085 // SDTR1 value for 66Mhz
- ori r6,r6,0x4005
- addis r7,0,0x03F8 // RTR value for 66Mhz
- b ..sdram_ok
-..chk_100:
- cmpi %cr0,0,r4,0x2
- bne ..chk_133
- addis r6,0,0x0086 // SDTR1 value for 100Mhz
- ori r6,r6,0x400D
- addis r7,0,0x05F0 // RTR value for 100Mhz
- b ..sdram_ok
-..chk_133:
- addis r6,0,0x0107 // SDTR1 value for 133Mhz
- ori r6,r6,0x4015
- addis r7,0,0x07F0 // RTR value for 133Mhz
-
-..sdram_ok:
- //-------------------------------------------------------------------
- // Set SDTR1
- //-------------------------------------------------------------------
- addi r4,0,mem_sdtr1
- mtdcr memcfga,r4
- mtdcr memcfgd,r6
-
- //-------------------------------------------------------------------
- // Set RTR
- //-------------------------------------------------------------------
- addi r4,0,mem_rtr
- mtdcr memcfga,r4
- mtdcr memcfgd,r7
-
- //-------------------------------------------------------------------
- // Delay to ensure 200usec have elapsed since reset. Assume worst
- // case that the core is running 200Mhz:
- // 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
- //-------------------------------------------------------------------
- addis r3,0,0x0000
- ori r3,r3,0xA000 // ensure 200usec have passed since reset
- mtctr r3
-..spinlp2:
- bdnz ..spinlp2 // spin loop
-
- //-------------------------------------------------------------------
- // Set memory controller options reg, MCOPT1.
- // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
- // read/prefetch.
- //-------------------------------------------------------------------
- addi r4,0,mem_mcopt1
- mtdcr memcfga,r4
- addis r4,0,0x8080 // set DC_EN=1
- ori r4,r4,0x0000
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Delay to ensure 10msec have elapsed since reset. This is
- // required for the MPC952 to stabalize. Assume worst
- // case that the core is running 200Mhz:
- // 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles
- // This delay should occur before accessing SDRAM.
- //-------------------------------------------------------------------
- addis r3,0,0x001E
- ori r3,r3,0x8480 // ensure 10msec have passed since reset
- mtctr r3
-..spinlp3:
- bdnz ..spinlp3 // spin loop
-
- //-------------------------------------------------------------------
- // Test if 64MByte is ok.
- //-------------------------------------------------------------------
- addis r3,0,MAGIC0@h
- ori r3,r3,MAGIC0@l
- addis r4,0,ADDR_ZERO@h
- ori r4,r4,ADDR_ZERO@l
- stw r3,0x00(r4) // store magic at 0
- addis r3,0,MAGIC1@h
- ori r3,r3,MAGIC1@l
- addis r4,0,ADDR_08MB@h
- ori r4,r4,ADDR_08MB@l
- stw r3,0x00(r4) // store magic at 8MB
- addis r3,0,MAGIC2@h
- ori r3,r3,MAGIC2@l
- addis r4,0,ADDR_16MB@h
- ori r4,r4,ADDR_16MB@l
- stw r3,0x00(r4) // store magic at 16MB
- addis r3,0,MAGIC3@h
- ori r3,r3,MAGIC3@l
- addis r4,0,ADDR_32MB@h
- ori r4,r4,ADDR_32MB@l
- stw r3,0x00(r4) // store magic at 32MB
-
- addis r3,0,MAGIC0@h
- ori r3,r3,MAGIC0@l
- addis r4,0,ADDR_ZERO@h
- ori r4,r4,ADDR_ZERO@l
- lwz r5,0x00(r4) // load from 0
- cmplw 0,r3,r5
- bne ..chk_32mb
- addis r3,0,MAGIC1@h
- ori r3,r3,MAGIC1@l
- addis r4,0,ADDR_08MB@h
- ori r4,r4,ADDR_08MB@l
- lwz r5,0x00(r4) // load from 8mb
- cmplw 0,r3,r5
- bne ..chk_32mb
- addis r3,0,MAGIC2@h
- ori r3,r3,MAGIC2@l
- addis r4,0,ADDR_16MB@h
- ori r4,r4,ADDR_16MB@l
- lwz r5,0x00(r4) // load from 8mb
- beq ..sdram_done
-
-..chk_32mb:
- //-------------------------------------------------------------------
- // Disable memory controller.
- //-------------------------------------------------------------------
- addi r4,0,mem_mcopt1
- mtdcr memcfga,r4
- addis r4,0,0x0000 // set DC_EN=0
- ori r4,r4,0x0000
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Set MB0CF for bank 0. (0-32MB) Address Mode 2 since 12x9(4)
- //-------------------------------------------------------------------
- addi r4,0,mem_mb0cf
- mtdcr memcfga,r4
- addis r4,0,0x0006
- ori r4,r4,0x2001
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Set memory controller options reg, MCOPT1.
- // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
- // read/prefetch.
- //-------------------------------------------------------------------
- addi r4,0,mem_mcopt1
- mtdcr memcfga,r4
- addis r4,0,0x8080 // set DC_EN=1
- ori r4,r4,0x0000
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Wait some time
- //-------------------------------------------------------------------
- addis r3,0,0x001E
- ori r3,r3,0x8480 // ensure 10msec have passed since reset
- mtctr r3
-..spinlp4:
- bdnz ..spinlp4 // spin loop
-
- //-------------------------------------------------------------------
- // Test if 32MByte is ok.
- //-------------------------------------------------------------------
- addis r3,0,MAGIC0@h
- ori r3,r3,MAGIC0@l
- addis r4,0,ADDR_ZERO@h
- ori r4,r4,ADDR_ZERO@l
- stw r3,0x00(r4) // store magic at 0
- addis r3,0,MAGIC1@h
- ori r3,r3,MAGIC1@l
- addis r4,0,ADDR_400@h
- ori r4,r4,ADDR_400@l
- stw r3,0x00(r4) // store magic at 0x400
- addis r3,0,MAGIC2@h
- ori r3,r3,MAGIC2@l
- addis r4,0,ADDR_08MB@h
- ori r4,r4,ADDR_08MB@l
- stw r3,0x00(r4) // store magic at 8MB
- addis r3,0,MAGIC3@h
- ori r3,r3,MAGIC3@l
- addis r4,0,ADDR_16MB@h
- ori r4,r4,ADDR_16MB@l
- stw r3,0x00(r4) // store magic at 16MB
-
- addis r3,0,MAGIC0@h
- ori r3,r3,MAGIC0@l
- addis r4,0,ADDR_ZERO@h
- ori r4,r4,ADDR_ZERO@l
- lwz r5,0x00(r4) // load from 0
- cmplw 0,r3,r5
- bne ..chk_16mb
- addis r3,0,MAGIC1@h
- ori r3,r3,MAGIC1@l
- addis r4,0,ADDR_400@h
- ori r4,r4,ADDR_400@l
- lwz r5,0x00(r4) // load from 0x400
- cmplw 0,r3,r5
- bne ..chk_16mb
- addis r3,0,MAGIC2@h
- ori r3,r3,MAGIC2@l
- addis r4,0,ADDR_08MB@h
- ori r4,r4,ADDR_08MB@l
- lwz r5,0x00(r4) // load from 8mb
- cmplw 0,r3,r5
- beq ..sdram_done
-
-..chk_16mb:
- //-------------------------------------------------------------------
- // Disable memory controller.
- //-------------------------------------------------------------------
- addi r4,0,mem_mcopt1
- mtdcr memcfga,r4
- addis r4,0,0x0000 // set DC_EN=0
- ori r4,r4,0x0000
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // 16 MB is left.
- // Set MB0CF for bank 0. (0-16MB) Address Mode 4 since 12x8(4)
- //-------------------------------------------------------------------
- addi r4,0,mem_mb0cf
- mtdcr memcfga,r4
- addis r4,0,0x0004
- ori r4,r4,0x6001
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Set memory controller options reg, MCOPT1.
- // Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst
- // read/prefetch.
- //-------------------------------------------------------------------
- addi r4,0,mem_mcopt1
- mtdcr memcfga,r4
- addis r4,0,0x8080 // set DC_EN=1
- ori r4,r4,0x0000
- mtdcr memcfgd,r4
-
- //-------------------------------------------------------------------
- // Wait some time
- //-------------------------------------------------------------------
- addis r3,0,0x001E
- ori r3,r3,0x8480 // ensure 10msec have passed since reset
- mtctr r3
-..spinlp5:
- bdnz ..spinlp5 // spin loop
-
-..sdram_done:
- mtlr r31 // restore lr
- blr
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
- board/esd/ocrtc/init.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
# endif
#endif
-extern u_long *my_sernum; /* from nx823.c */
-
/*-----------------------------------------------------------------------
* Protection Flags:
*/
port_width = 4;
#endif
-#if 0
- /* save sernum if needed */
- if (addr >= CFG_FLASH_SN_SECTOR && addr < CFG_FLASH_SN_BASE)
- {
- u_long dest = CFG_FLASH_SN_BASE;
- u_short *sn = (u_short *)my_sernum;
-
- printf("(saving sernum)");
- for (i=0; i<4; i++)
- {
- if ((rc = write_data(info, dest, sn[i])) != 0) {
- return (rc);
- }
- dest += port_width;
- }
- }
-#endif
-
/*
* handle unaligned start bytes
*/
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
&flash_info[0]);
+#ifdef CFG_ENV_ADDR_REDUND
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR_REDUND,
+ CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
+ &flash_info[0]);
+#endif
+
return size;
}
lib_ppc/time.o (.text)
. = env_offset;
- common/environment.o (.text)
+ common/environment.o (.ppcenv)
*(.text)
*(.fixup)
cmd_eeprom.o cmd_elf.o cmd_fdc.o cmd_flash.o \
cmd_fpga.o cmd_i2c.o cmd_ide.o cmd_immap.o \
cmd_jffs2.o cmd_mem.o cmd_mii.o cmd_misc.o \
- cmd_net.o cmd_nvedit.o cmd_pci.o cmd_pcmcia.o \
+ cmd_net.o cmd_nvedit.o env_common.o \
+ env_flash.o env_eeprom.o env_nvram.o env_nowhere.o \
+ cmd_pci.o cmd_pcmcia.o \
cmd_reginfo.o cmd_scsi.o cmd_usb.o \
command.o console.o devices.o dlmalloc.o \
docecc.o environment.o flash.o fpga.o \
rcode = flash_sect_protect (p, addr_first, addr_last);
return rcode;
}
+
+
int flash_sect_protect (int p, ulong addr_first, ulong addr_last)
{
flash_info_t *info;
**************************************************************************
*/
-/*
- * 09-18-2001 Andreas Heppel, Sysgo RTS GmbH <aheppel@sysgo.de>
- *
- * It might not be possible in all cases to use 'memcpy()' to copy
- * the environment to NVRAM, as the NVRAM might not be mapped into
- * the memory space. (I.e. this is the case for the BAB750). In those
- * cases it might be possible to access the NVRAM using a different
- * method. For example, the RTC on the BAB750 is accessible in IO
- * space using its address and data registers. To enable usage of
- * NVRAM in those cases I invented the functions 'nvram_read()' and
- * 'nvram_write()', which will be activated upon the configuration
- * #define CFG_NVRAM_ACCESS_ROUTINE. Note, that those functions are
- * strongly dependent on the used HW, and must be redefined for each
- * board that wants to use them.
- */
-
#include <common.h>
#include <command.h>
#include <environment.h>
#include <net.h>
#endif
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-# include <status_led.h>
-# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
-#else
-# define SHOW_BOOT_PROGRESS(arg)
-#endif
-
-/*
- * Table with supported baudrates (defined in config_xyz.h)
- */
-static const unsigned long baudrate_table[] = CFG_BAUDRATE_TABLE;
-#define N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0]))
-
-/*---------------------------------------------------------------------*/
-#undef DEBUG_ENV
-
-#ifdef DEBUG_ENV
-#define DEBUGF(fmt,args...) printf(fmt ,##args)
-#else
-#define DEBUGF(fmt,args...)
-#endif
-/*---------------------------------------------------------------------*/
-
-
-#if !defined(ENV_IS_EMBEDDED)
-#include <malloc.h>
-#endif
-
-/*--- NVRAM ----------------------------------------------------------*/
-#ifdef CFG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */
-
-#ifdef CFG_NVRAM_ACCESS_ROUTINE
-
-static env_t *env_ptr = NULL;
-void *nvram_read(void *dest, const long src, size_t count);
-void nvram_write(long dest, const void *src, size_t count);
-
-#else
-
-static env_t *env_ptr = (env_t *)CFG_ENV_ADDR;
-
-#endif
-
-/*--- EEPROM ----------------------------------------------------------*/
-#elif defined(CFG_ENV_IS_IN_EEPROM) /* Environment is in EEPROM */
-static env_t *env_ptr = NULL;
-
-/*--- FLASH ----------------------------------------------------------*/
-#elif defined(CFG_ENV_IS_IN_FLASH) /* Environment is in Flash */
-# if defined(ENV_IS_EMBEDDED) /* embedded within PPCBoot */
-
-extern uchar environment[];
-static env_t *env_ptr = (env_t *)(&environment[0]);
-# if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH))
-static uchar *flash_addr = &environment[0];
-# endif /* ENV, FLASH */
-
-# else /* !ENV_IS_EMBEDDED*/ /* not embedded within PPCBoot */
-static env_t *env_ptr = (env_t *)CFG_ENV_ADDR;
-/* need both ENV and flash */
-# if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH))
-static uchar *flash_addr = (uchar *)CFG_ENV_ADDR;
-# endif /* ENV, FLASH */
-
-# endif /* ENV_IS_EMBEDDED */
-
-/*--- NOWHERE ---------------------------------------------------------*/
-#elif defined(CFG_ENV_IS_NOWHERE) /* Environment is nowhere */
-static env_t *env_ptr = NULL;
-
-#else
+#if !defined(CFG_ENV_IS_IN_NVRAM) && !defined(CFG_ENV_IS_IN_EEPROM) && !defined(CFG_ENV_IS_IN_FLASH) && !defined(CFG_ENV_IS_NOWHERE)
# error Define one of CFG_ENV_IS_IN_NVRAM, CFG_ENV_IS_IN_EEPROM, CFG_ENV_IS_IN_FLASH, CFG_ENV_IS_NOWHERE
-#endif /* CFG_ENV_IS_IN_FLASH */
-
-/*----------------------------------------------------------------------*/
+#endif
-/************************************************************************
- * Default settings to be used when no valid environment is found
- */
#define XMK_STR(x) #x
#define MK_STR(x) XMK_STR(x)
-static uchar default_environment[] = {
-#ifdef CONFIG_BOOTARGS
- "bootargs=" CONFIG_BOOTARGS "\0"
-#endif
-#ifdef CONFIG_BOOTCOMMAND
- "bootcmd=" CONFIG_BOOTCOMMAND "\0"
-#endif
-#ifdef CONFIG_RAMBOOTCOMMAND
- "ramboot=" CONFIG_RAMBOOTCOMMAND "\0"
-#endif
-#ifdef CONFIG_NFSBOOTCOMMAND
- "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0"
-#endif
-#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
- "bootdelay=" MK_STR(CONFIG_BOOTDELAY) "\0"
-#endif
-#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
- "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"
-#endif
-#ifdef CONFIG_LOADS_ECHO
- "loads_echo=" MK_STR(CONFIG_LOADS_ECHO) "\0"
-#endif
-#ifdef CONFIG_ETHADDR
- "ethaddr=" MK_STR(CONFIG_ETHADDR) "\0"
-#endif
-#ifdef CONFIG_ETH1ADDR
- "eth1addr=" MK_STR(CONFIG_ETH1ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH2ADDR
- "eth2addr=" MK_STR(CONFIG_ETH2ADDR) "\0"
-#endif
-#ifdef CONFIG_IPADDR
- "ipaddr=" MK_STR(CONFIG_IPADDR) "\0"
-#endif
-#ifdef CONFIG_SERVERIP
- "serverip=" MK_STR(CONFIG_SERVERIP) "\0"
-#endif
-#ifdef CFG_AUTOLOAD
- "autoload=" CFG_AUTOLOAD "\0"
-#endif
-#ifdef CONFIG_PREBOOT
- "preboot=" CONFIG_PREBOOT "\0"
-#endif
-#ifdef CONFIG_ROOTPATH
- "rootpath=" MK_STR(CONFIG_ROOTPATH) "\0"
-#endif
-#ifdef CONFIG_GATEWAYIP
- "gatewayip=" MK_STR(CONFIG_GATEWAYIP) "\0"
-#endif
-#ifdef CONFIG_NETMASK
- "netmask=" MK_STR(CONFIG_NETMASK) "\0"
-#endif
-#ifdef CONFIG_HOSTNAME
- "hostname=" MK_STR(CONFIG_HOSTNAME) "\0"
-#endif
-#ifdef CONFIG_BOOTFILE
- "bootfile=" MK_STR(CONFIG_BOOTFILE) "\0"
-#endif
-#ifdef CONFIG_LOADADDR
- "loadaddr=" MK_STR(CONFIG_LOADADDR) "\0"
-#endif
-#ifdef CONFIG_CLOCKS_IN_MHZ
- "clocks_in_mhz=1\0"
-#endif
-#ifdef CONFIG_EXTRA_ENV_SETTINGS
- CONFIG_EXTRA_ENV_SETTINGS
-#endif
- "\0"
-};
-
-
/************************************************************************
************************************************************************/
-static int envmatch (uchar *, int);
-
-/************************************************************************
-************************************************************************/
-
-#ifdef CFG_ENV_IS_IN_EEPROM
-static uchar get_env_char_eeprom(int);
-#endif
-#if defined(CFG_ENV_IS_IN_NVRAM) && defined(CFG_NVRAM_ACCESS_ROUTINE)
-static uchar get_env_char_nvram(int);
-#endif
-static uchar get_env_char_memory(int);
-static uchar *get_env_addr_memory(int);
-
/* Function that returns a character from the environment */
-static uchar (*get_env_char)(int) =
-#ifdef CFG_ENV_IS_IN_EEPROM
- get_env_char_eeprom;
-#elif defined(CFG_ENV_IS_IN_NVRAM) && defined(CFG_NVRAM_ACCESS_ROUTINE)
- get_env_char_nvram;
-#else
- get_env_char_memory;
-#endif
+extern uchar (*env_get_char)(int);
+
/* Function that returns a pointer to a value from the environment */
/* (Only memory version supported / needed). */
-static uchar *(*get_env_addr)(int) = get_env_addr_memory;
+extern uchar *env_get_addr(int);
-/************************************************************************
-************************************************************************/
-
-void env_relocate (void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- DEBUGF ("%s[%d] offset = 0x%lx\n", __FUNCTION__,__LINE__,
- gd->reloc_off);
-#if !defined(ENV_IS_EMBEDDED) || defined(CFG_ENV_IS_IN_NVRAM)
- /*
- * We must allocate a buffer for the environment
- * (We _could_ work directly in NVRAM, however we want
- * to modify persistent values only using "saveenv",
- * so we need a RAM copy here, too.
- */
- env_ptr = (env_t *)malloc (CFG_ENV_SIZE);
- DEBUGF ("%s[%d] malloced ENV at %p\n", __FUNCTION__,__LINE__,env_ptr);
-#else /* ENV_IS_EMBEDDED */
- /*
- * The environment buffer is embedded with the text segment,
- * just relocate the environment pointer
- */
- env_ptr = (env_t *)((ulong)env_ptr + gd->reloc_off);
- DEBUGF ("%s[%d] embedded ENV at %p\n", __FUNCTION__,__LINE__,env_ptr);
-#endif
+/* Function that updates CRC of the enironment */
+extern void env_crc_update (void);
- /*
- * Update all function pointers
- * After relocation to RAM, we can always use the "memory" functions
- */
- get_env_char = get_env_char_memory;
- get_env_addr = get_env_addr_memory;
-
- if (gd->env_valid == 0) {
-#if defined(CONFIG_GTH) || defined(CFG_ENV_IS_NOWHERE) /* Environment not changable */
- puts ("Using default environment\n\n");
-#else
- puts ("*** Warning - bad CRC, using default environment\n\n");
- SHOW_BOOT_PROGRESS (-1);
-#endif
- /*
- * TODO: We should check here that the
- * default environment does not overflow the buffer.
- */
- memset (env_ptr, 0, sizeof(env_t));
- memcpy (env_ptr->data,
- default_environment,
- sizeof(default_environment));
- env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE);
- gd->env_valid = 1;
- }
-#if !defined(ENV_IS_EMBEDDED)
- else {
- DEBUGF ("%s[%d] ENV is valid\n", __FUNCTION__,__LINE__);
-# if defined(CFG_ENV_IS_IN_EEPROM)
- DEBUGF ("%s[%d] read ENV from EEPROM\n", __FUNCTION__,__LINE__);
- eeprom_read (CFG_DEF_EEPROM_ADDR, CFG_ENV_OFFSET,
- (uchar *)env_ptr,
- CFG_ENV_SIZE);
-# elif defined(CFG_ENV_IS_IN_NVRAM) && defined(CFG_NVRAM_ACCESS_ROUTINE)
- DEBUGF ("%s[%d] read ENV from NVRAM\n", __FUNCTION__,__LINE__);
- nvram_read(env_ptr, CFG_ENV_ADDR, CFG_ENV_SIZE);
-# elif !defined(CFG_ENV_IS_NOWHERE)
- DEBUGF ("%s[%d] read ENV from NVRAM/FLASH\n",__FUNCTION__,__LINE__);
- memcpy (env_ptr, (void*)CFG_ENV_ADDR, CFG_ENV_SIZE);
-# endif
- }
-#endif
- gd->env_addr = (ulong)&(env_ptr->data);
-}
/************************************************************************
************************************************************************/
-/*
- * Utility function when we can read directly from memory
- */
-static uchar get_env_char_memory (int index)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- if (gd->env_valid) {
- return ( *((uchar *)(gd->env_addr + index)) );
- } else {
- return ( default_environment[index] );
- }
-}
-
-
-static uchar *get_env_addr_memory(int index)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- if (gd->env_valid) {
- return ( ((uchar *)(gd->env_addr + index)) );
- } else {
- return (&default_environment[index]);
- }
-}
-
-#if defined(CFG_ENV_IS_IN_NVRAM) && defined(CFG_NVRAM_ACCESS_ROUTINE)
-static uchar get_env_char_nvram(int index)
-{
- DECLARE_GLOBAL_DATA_PTR;
- uchar c;
-
- /* if the NVRAM crc was bad, use the default environment */
- if (gd->env_valid)
- nvram_read(&c, CFG_ENV_ADDR+index, 1);
- else
- c = default_environment[index];
-
- return c;
-}
-#endif
+static int envmatch (uchar *, int);
-#ifdef CFG_ENV_IS_IN_EEPROM
/*
- * Utility function when we have to read from serial device
+ * Table with supported baudrates (defined in config_xyz.h)
*/
-static uchar get_env_char_eeprom (int index)
-{
- DECLARE_GLOBAL_DATA_PTR;
- uchar c;
-
- /* if the EEPROM crc was bad, use the default environment */
- if (gd->env_valid)
- {
- eeprom_read (CFG_DEF_EEPROM_ADDR,
- CFG_ENV_OFFSET+index+offsetof(env_t,data),
- &c, 1);
- } else {
- c = default_environment[index];
- }
+static const unsigned long baudrate_table[] = CFG_BAUDRATE_TABLE;
+#define N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0]))
- return (c);
-}
-#endif /* CFG_ENV_IS_IN_EEPROM */
/************************************************************************
* Command interface: print one or all environment variables
int rcode = 0;
if (argc == 1) { /* Print all env variables */
- for (i=0; get_env_char(i) != '\0'; i=nxt+1) {
- for (nxt=i; get_env_char(nxt) != '\0'; ++nxt)
+ for (i=0; env_get_char(i) != '\0'; i=nxt+1) {
+ for (nxt=i; env_get_char(nxt) != '\0'; ++nxt)
;
for (k=i; k<nxt; ++k)
- putc(get_env_char(k));
+ putc(env_get_char(k));
putc ('\n');
if (ctrlc()) {
k = -1;
- for (j=0; get_env_char(j) != '\0'; j=nxt+1) {
+ for (j=0; env_get_char(j) != '\0'; j=nxt+1) {
- for (nxt=j; get_env_char(nxt) != '\0'; ++nxt)
+ for (nxt=j; env_get_char(nxt) != '\0'; ++nxt)
;
k = envmatch(name, j);
if (k < 0) {
puts (name);
putc ('=');
while (k < nxt)
- putc(get_env_char(k++));
+ putc(env_get_char(k++));
putc ('\n');
break;
}
uchar *name;
bd_t *bd = gd->bd;
- uchar *env_data = get_env_addr(0);
+ uchar *env_data = env_get_addr(0);
if (!env_data) /* need copy in RAM */
return 1;
if ( (strcmp (name, "serial#") == 0) ||
((strcmp (name, "ethaddr") == 0)
#if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR)
- && (strcmp (get_env_addr(oldval),MK_STR(CONFIG_ETHADDR)) != 0)
+ && (strcmp (env_get_addr(oldval),MK_STR(CONFIG_ETHADDR)) != 0)
#endif /* CONFIG_OVERWRITE_ETHADDR_ONCE && CONFIG_ETHADDR */
) ) {
printf ("Can't overwrite \"%s\"\n", name);
/* Delete only ? */
if ((argc < 3) || argv[2] == NULL) {
- /* Update CRC */
- env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE);
-
+ env_crc_update ();
return 0;
}
*++env = '\0';
/* Update CRC */
- env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE);
+ env_crc_update ();
/*
* Some variables should be updated when the corresponding
{
int i, nxt;
- for (i=0; get_env_char(i) != '\0'; i=nxt+1) {
+ for (i=0; env_get_char(i) != '\0'; i=nxt+1) {
int val;
- for (nxt=i; get_env_char(nxt) != '\0'; ++nxt) {
+ for (nxt=i; env_get_char(nxt) != '\0'; ++nxt) {
if (nxt >= CFG_ENV_SIZE) {
return (NULL);
}
}
if ((val=envmatch(name, i)) < 0)
continue;
- return (get_env_addr(val));
+ return (env_get_addr(val));
}
return (NULL);
{
int i, nxt;
- for (i=0; get_env_char(i) != '\0'; i=nxt+1) {
+ for (i=0; env_get_char(i) != '\0'; i=nxt+1) {
int val, n;
- for (nxt=i; get_env_char(nxt) != '\0'; ++nxt) {
+ for (nxt=i; env_get_char(nxt) != '\0'; ++nxt) {
if (nxt >= CFG_ENV_SIZE) {
return (-1);
}
continue;
/* found; copy out */
n = 0;
- while ((len > n++) && (*buf++ = get_env_char(val++)) != '\0')
+ while ((len > n++) && (*buf++ = env_get_char(val++)) != '\0')
;
if (len == n)
*buf = '\0';
return (-1);
}
+#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \
+ ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \
+ (CFG_CMD_ENV|CFG_CMD_FLASH))
+int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ extern char * env_name_spec;
+
+ printf ("Saving Environment to %s...\n", env_name_spec);
+
+ return (saveenv() ? 1 : 0);
+}
+#endif
+
/************************************************************************
* Match a name / name=value pair
envmatch (uchar *s1, int i2)
{
- while (*s1 == get_env_char(i2++))
+ while (*s1 == env_get_char(i2++))
if (*s1++ == '=')
return(i2);
- if (*s1 == '\0' && get_env_char(i2-1) == '=')
+ if (*s1 == '\0' && env_get_char(i2-1) == '=')
return(i2);
return(-1);
}
-
-#define SAVESTR(type) "Saving Environment to " #type "...\n"
-
-#ifdef CFG_ENV_IS_IN_NVRAM
-#define NVRAM_SAVESTR SAVESTR(NVRAM)
-
-int saveenv(void)
-{
- int rcode = 0;
-
-#ifdef CFG_NVRAM_ACCESS_ROUTINE
- nvram_write(CFG_ENV_ADDR, env_ptr, CFG_ENV_SIZE);
-#else
- if (memcpy ((char *)CFG_ENV_ADDR, env_ptr, CFG_ENV_SIZE) == NULL)
- rcode = 1 ;
-#endif
- return rcode;
-}
-
-#elif defined(CFG_ENV_IS_IN_EEPROM)
-#define NVRAM_SAVESTR SAVESTR(EEPROM)
-
-int saveenv(void)
-{
- return (eeprom_write (CFG_DEF_EEPROM_ADDR,
- CFG_ENV_OFFSET,
- (uchar *)env_ptr, CFG_ENV_SIZE)
- );
-}
-
-#else /* !CFG_ENV_IS_IN_NVRAM, !CFG_ENV_IS_IN_EEPROM => Must be flash, then */
-#define NVRAM_SAVESTR SAVESTR(Flash)
-
-/* need both ENV and flash */
-#if ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH))
-
-int saveenv(void)
-{
- int len, rc;
- ulong end_addr;
- uchar *flash_sect_addr;
-#if defined(CFG_ENV_SECT_SIZE) && (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE)
- uchar *flash_offset;
- uchar env_buffer[CFG_ENV_SECT_SIZE];
-#else
- uchar *env_buffer = (char *)env_ptr;
-#endif /* CFG_ENV_SECT_SIZE */
- int rcode = 0;
-
-#if defined(CFG_ENV_SECT_SIZE) && (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE)
-
- flash_offset = (uchar *)(((ulong)flash_addr) & (CFG_ENV_SECT_SIZE-1));
- flash_sect_addr = (uchar *)(((ulong)flash_addr) & ~(CFG_ENV_SECT_SIZE-1));
-
- /* copy old contents to temporary buffer */
- memcpy (env_buffer, flash_sect_addr, CFG_ENV_SECT_SIZE);
-
- /* copy current environment to temporary buffer */
- memcpy ((uchar *)((unsigned long)env_buffer + (unsigned long)flash_offset),
- env_ptr,
- CFG_ENV_SIZE);
-
- len = CFG_ENV_SECT_SIZE;
-#else
- flash_sect_addr = flash_addr;
- len = CFG_ENV_SIZE;
-#endif /* CFG_ENV_SECT_SIZE */
-
-#ifndef CONFIG_INFERNO
- end_addr = (ulong)flash_sect_addr + len - 1;
-#else
- /* this is the last sector, and the size is hardcoded here */
- /* otherwise we will get stack problems on loading 128 KB environment */
- end_addr = (ulong)flash_sect_addr + 0x20000 - 1;
-#endif
-
- if (flash_sect_protect (0, (ulong)flash_sect_addr, end_addr))
- return 1;
-
- puts ("Erasing Flash...");
- if (flash_sect_erase ((ulong)flash_sect_addr, end_addr))
- return 1;
-
- puts ("Writing to Flash... ");
- rc = flash_write(env_buffer, (ulong)flash_sect_addr, len);
- if (rc != 0) {
- flash_perror (rc);
- rcode = 1;
- } else {
- puts ("done\n");
- }
-
- /* try to re-protect */
- (void) flash_sect_protect (1, (ulong)flash_sect_addr, end_addr);
- return rcode;
-}
-
-#endif /* CFG_CMD_ENV + CFG_CMD_FLASH */
-
-#endif /* CFG_ENV_IS_IN_NVRAM */
-
-#if defined(CFG_ENV_IS_IN_NVRAM) || defined(CFG_ENV_IS_IN_EEPROM) || \
- ((CONFIG_COMMANDS & (CFG_CMD_ENV|CFG_CMD_FLASH)) == \
- (CFG_CMD_ENV|CFG_CMD_FLASH))
-int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- puts (NVRAM_SAVESTR);
-
- return (saveenv() ? 1 : 0);
-}
-#endif
-
-/************************************************************************
- * Initialize Environment use
- *
- * We are still running from ROM, so data use is limited
- */
-#ifndef CFG_ENV_IS_IN_EEPROM
-
-#if defined(CFG_ENV_IS_IN_NVRAM) && defined(CFG_NVRAM_ACCESS_ROUTINE)
-
-int env_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- ulong crc;
- uchar data[ENV_SIZE];
- nvram_read (&crc, CFG_ENV_ADDR, sizeof(ulong));
- nvram_read (data, CFG_ENV_ADDR+sizeof(ulong), ENV_SIZE);
-
- if (crc32(0, data, ENV_SIZE) == crc) {
- gd->env_addr = (ulong)CFG_ENV_ADDR + sizeof(long);
- gd->env_valid = 1;
- } else {
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = 0;
- }
-
- return (0);
-}
-#else
-int env_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
- gd->env_addr = (ulong)&(env_ptr->data);
- gd->env_valid = 1;
- } else {
- gd->env_addr = (ulong)&default_environment[0];
- gd->env_valid = 0;
- }
-
- return (0);
-}
-#endif /* defined(CFG_ENV_IS_IN_NVRAM) && defined(CFG_NVRAM_ACCESS_ROUTINE) */
-
-#else /* CFG_ENV_IS_IN_EEPROM */
-/*
- * Use a (moderately small) buffer on the stack
- */
-int env_init(void)
-{
- DECLARE_GLOBAL_DATA_PTR;
-
- ulong crc, len, new;
- unsigned off;
- uchar buf[64];
-
- eeprom_init (); /* prepare for EEPROM read/write */
-
- /* read old CRC */
- eeprom_read (CFG_DEF_EEPROM_ADDR,
- CFG_ENV_OFFSET+offsetof(env_t,crc),
- (uchar *)&crc, sizeof(ulong));
-
- new = 0;
- len = ENV_SIZE;
- off = offsetof(env_t,data);
- while (len > 0) {
- int n = (len > sizeof(buf)) ? sizeof(buf) : len;
-
- eeprom_read (CFG_DEF_EEPROM_ADDR, CFG_ENV_OFFSET+off, buf, n);
- new = crc32 (new, buf, n);
- len -= n;
- off += n;
- }
-
-
- if (crc == new) {
- gd->env_addr = offsetof(env_t,data);
- gd->env_valid = 1;
- } else {
- gd->env_addr = 0;
- gd->env_valid = 0;
- }
-
- return (0);
-}
-#endif /* CFG_ENV_IS_IN_EEPROM */
--- /dev/null
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <cmd_nvedit.h>
+#include <linux/stddef.h>
+#include <malloc.h>
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# include <status_led.h>
+# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+#undef DEBUG_ENV
+#ifdef DEBUG_ENV
+#define DEBUGF(fmt,args...) printf(fmt ,##args)
+#else
+#define DEBUGF(fmt,args...)
+#endif
+
+extern env_t *env_ptr;
+
+extern void env_relocate_spec (void);
+extern uchar env_get_char_spec(int);
+
+static uchar env_get_char_init (int index);
+uchar (*env_get_char)(int) = env_get_char_init;
+
+/************************************************************************
+ * Default settings to be used when no valid environment is found
+ */
+#define XMK_STR(x) #x
+#define MK_STR(x) XMK_STR(x)
+
+uchar default_environment[] = {
+#ifdef CONFIG_BOOTARGS
+ "bootargs=" CONFIG_BOOTARGS "\0"
+#endif
+#ifdef CONFIG_BOOTCOMMAND
+ "bootcmd=" CONFIG_BOOTCOMMAND "\0"
+#endif
+#ifdef CONFIG_RAMBOOTCOMMAND
+ "ramboot=" CONFIG_RAMBOOTCOMMAND "\0"
+#endif
+#ifdef CONFIG_NFSBOOTCOMMAND
+ "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0"
+#endif
+#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
+ "bootdelay=" MK_STR(CONFIG_BOOTDELAY) "\0"
+#endif
+#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
+ "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"
+#endif
+#ifdef CONFIG_LOADS_ECHO
+ "loads_echo=" MK_STR(CONFIG_LOADS_ECHO) "\0"
+#endif
+#ifdef CONFIG_ETHADDR
+ "ethaddr=" MK_STR(CONFIG_ETHADDR) "\0"
+#endif
+#ifdef CONFIG_ETH1ADDR
+ "eth1addr=" MK_STR(CONFIG_ETH1ADDR) "\0"
+#endif
+#ifdef CONFIG_ETH2ADDR
+ "eth2addr=" MK_STR(CONFIG_ETH2ADDR) "\0"
+#endif
+#ifdef CONFIG_IPADDR
+ "ipaddr=" MK_STR(CONFIG_IPADDR) "\0"
+#endif
+#ifdef CONFIG_SERVERIP
+ "serverip=" MK_STR(CONFIG_SERVERIP) "\0"
+#endif
+#ifdef CFG_AUTOLOAD
+ "autoload=" CFG_AUTOLOAD "\0"
+#endif
+#ifdef CONFIG_PREBOOT
+ "preboot=" CONFIG_PREBOOT "\0"
+#endif
+#ifdef CONFIG_ROOTPATH
+ "rootpath=" MK_STR(CONFIG_ROOTPATH) "\0"
+#endif
+#ifdef CONFIG_GATEWAYIP
+ "gatewayip=" MK_STR(CONFIG_GATEWAYIP) "\0"
+#endif
+#ifdef CONFIG_NETMASK
+ "netmask=" MK_STR(CONFIG_NETMASK) "\0"
+#endif
+#ifdef CONFIG_HOSTNAME
+ "hostname=" MK_STR(CONFIG_HOSTNAME) "\0"
+#endif
+#ifdef CONFIG_BOOTFILE
+ "bootfile=" MK_STR(CONFIG_BOOTFILE) "\0"
+#endif
+#ifdef CONFIG_LOADADDR
+ "loadaddr=" MK_STR(CONFIG_LOADADDR) "\0"
+#endif
+#ifdef CONFIG_CLOCKS_IN_MHZ
+ "clocks_in_mhz=1\0"
+#endif
+#ifdef CONFIG_EXTRA_ENV_SETTINGS
+ CONFIG_EXTRA_ENV_SETTINGS
+#endif
+ "\0"
+};
+
+
+void env_crc_update (void)
+{
+ env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE);
+}
+
+static uchar env_get_char_init (int index)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ uchar c;
+
+ /* if crc was bad, use the default environment */
+ if (gd->env_valid)
+ {
+ c = env_get_char_spec(index);
+ } else {
+ c = default_environment[index];
+ }
+
+ return (c);
+}
+
+uchar env_get_char_memory (int index)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ if (gd->env_valid) {
+ return ( *((uchar *)(gd->env_addr + index)) );
+ } else {
+ return ( default_environment[index] );
+ }
+}
+
+uchar *env_get_addr (int index)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ if (gd->env_valid) {
+ return ( ((uchar *)(gd->env_addr + index)) );
+ } else {
+ return (&default_environment[index]);
+ }
+}
+
+void env_relocate (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ DEBUGF ("%s[%d] offset = 0x%lx\n", __FUNCTION__,__LINE__,
+ gd->reloc_off);
+
+#ifdef ENV_IS_EMBEDDED
+ /*
+ * The environment buffer is embedded with the text segment,
+ * just relocate the environment pointer
+ */
+ env_ptr = (env_t *)((ulong)env_ptr + gd->reloc_off);
+ DEBUGF ("%s[%d] embedded ENV at %p\n", __FUNCTION__,__LINE__,env_ptr);
+#else
+ /*
+ * We must allocate a buffer for the environment
+ */
+ env_ptr = (env_t *)malloc (CFG_ENV_SIZE);
+ DEBUGF ("%s[%d] malloced ENV at %p\n", __FUNCTION__,__LINE__,env_ptr);
+#endif
+
+ /*
+ * After relocation to RAM, we can always use the "memory" functions
+ */
+ env_get_char = env_get_char_memory;
+
+ if (gd->env_valid == 0) {
+#if defined(CONFIG_GTH) || defined(CFG_ENV_IS_NOWHERE) /* Environment not changable */
+ puts ("Using default environment\n\n");
+#else
+ puts ("*** Warning - bad CRC, using default environment\n\n");
+ SHOW_BOOT_PROGRESS (-1);
+#endif
+
+ if (sizeof(default_environment) > ENV_SIZE)
+ {
+ puts ("*** Error - default environment is too large\n\n");
+ return;
+ }
+
+ memset (env_ptr, 0, sizeof(env_t));
+ memcpy (env_ptr->data,
+ default_environment,
+ sizeof(default_environment));
+ env_ptr->flags = 0xFF;
+ env_crc_update ();
+ gd->env_valid = 1;
+ }
+ else {
+ env_relocate_spec ();
+ }
+ gd->env_addr = (ulong)&(env_ptr->data);
+}
--- /dev/null
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CFG_ENV_IS_IN_EEPROM) /* Environment is in EEPROM */
+
+#include <command.h>
+#include <environment.h>
+#include <cmd_nvedit.h>
+#include <linux/stddef.h>
+#include <malloc.h>
+
+env_t *env_ptr = NULL;
+
+char * env_name_spec = "EEPROM";
+
+extern uchar (*env_get_char)(int);
+extern uchar env_get_char_memory (int index);
+
+
+uchar env_get_char_spec (int index)
+{
+ uchar c;
+
+ eeprom_read (CFG_DEF_EEPROM_ADDR,
+ CFG_ENV_OFFSET+index+offsetof(env_t,data),
+ &c, 1);
+
+ return (c);
+}
+
+void env_relocate_spec (void)
+{
+ eeprom_read (CFG_DEF_EEPROM_ADDR,
+ CFG_ENV_OFFSET,
+ (uchar*)env_ptr,
+ CFG_ENV_SIZE);
+}
+
+int saveenv(void)
+{
+ return eeprom_write (CFG_DEF_EEPROM_ADDR,
+ CFG_ENV_OFFSET,
+ (uchar *)env_ptr,
+ CFG_ENV_SIZE);
+}
+
+/************************************************************************
+ * Initialize Environment use
+ *
+ * We are still running from ROM, so data use is limited
+ * Use a (moderately small) buffer on the stack
+ */
+int env_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ ulong crc, len, new;
+ unsigned off;
+ uchar buf[64];
+
+ eeprom_init (); /* prepare for EEPROM read/write */
+
+ /* read old CRC */
+ eeprom_read (CFG_DEF_EEPROM_ADDR,
+ CFG_ENV_OFFSET+offsetof(env_t,crc),
+ (uchar *)&crc, sizeof(ulong));
+
+ new = 0;
+ len = ENV_SIZE;
+ off = offsetof(env_t,data);
+ while (len > 0) {
+ int n = (len > sizeof(buf)) ? sizeof(buf) : len;
+
+ eeprom_read (CFG_DEF_EEPROM_ADDR, CFG_ENV_OFFSET+off, buf, n);
+ new = crc32 (new, buf, n);
+ len -= n;
+ off += n;
+ }
+
+ if (crc == new) {
+ gd->env_addr = offsetof(env_t,data);
+ gd->env_valid = 1;
+ } else {
+ gd->env_addr = 0;
+ gd->env_valid = 0;
+ }
+
+ return (0);
+}
+
+#endif /* CFG_ENV_IS_IN_EEPROM */
--- /dev/null
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CFG_ENV_IS_IN_FLASH) /* Environment is in Flash */
+
+#include <command.h>
+#include <environment.h>
+#include <cmd_nvedit.h>
+#include <linux/stddef.h>
+
+#if ((CONFIG_COMMANDS&(CFG_CMD_ENV|CFG_CMD_FLASH)) == (CFG_CMD_ENV|CFG_CMD_FLASH))
+#define CMD_SAVEENV
+#elif defined(CFG_ENV_ADDR_REDUND)
+#error Cannot use CFG_ENV_ADDR_REDUND without CFG_CMD_ENV & CFG_CMD_FLASH
+#endif
+
+#if defined(CFG_ENV_SECT_SIZE) && (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE) && \
+ defined(CFG_ENV_ADDR_REDUND)
+#error CFG_ENV_ADDR_REDUND should not be used when CFG_ENV_SECT_SIZE > CFG_ENV_SIZE
+#endif
+
+#if defined(CFG_ENV_SIZE_REDUND) && (CFG_ENV_SIZE_REDUND < CFG_ENV_SIZE)
+#error CFG_ENV_SIZE_REDUND should not be less then CFG_ENV_SIZE
+#endif
+
+#ifdef CONFIG_INFERNO
+#error CFG_ENV_ADDR_REDUND is not implemented for CONFIG_INFERNO
+#endif
+
+char * env_name_spec = "Flash";
+
+#ifdef ENV_IS_EMBEDDED
+
+extern uchar environment[];
+env_t *env_ptr = (env_t *)(&environment[0]);
+
+#ifdef CMD_SAVEENV
+static env_t *flash_addr = (env_t *)(&environment[0]);
+#endif
+
+#else /* ! ENV_IS_EMBEDDED */
+
+env_t *env_ptr = (env_t *)CFG_ENV_ADDR;
+#ifdef CMD_SAVEENV
+static env_t *flash_addr = (env_t *)CFG_ENV_ADDR;
+#endif
+
+#endif /* ENV_IS_EMBEDDED */
+
+#ifdef CFG_ENV_ADDR_REDUND
+static env_t *flash_addr_new = (env_t *)CFG_ENV_ADDR_REDUND;
+
+static ulong end_addr = CFG_ENV_ADDR + CFG_ENV_SIZE - 1;
+static ulong end_addr_new = CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1;
+
+static uchar active_flag = 1;
+static uchar obsolete_flag = 0;
+#endif
+
+extern uchar default_environment[];
+extern int default_environment_size;
+
+
+uchar env_get_char_spec (int index)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ return ( *((uchar *)(gd->env_addr + index)) );
+}
+
+#ifdef CFG_ENV_ADDR_REDUND
+
+int env_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ int crc1_ok =
+ (crc32(0, flash_addr->data, ENV_SIZE) == flash_addr->crc);
+ int crc2_ok =
+ (crc32(0, flash_addr_new->data, ENV_SIZE) == flash_addr_new->crc);
+
+ uchar flag1 = flash_addr->flags;
+ uchar flag2 = flash_addr_new->flags;
+
+ ulong addr_default = (ulong)&default_environment[0];
+ ulong addr1 = (ulong)&(flash_addr->data);
+ ulong addr2 = (ulong)&(flash_addr_new->data);
+
+ if (crc1_ok && ! crc2_ok)
+ {
+ gd->env_addr = addr1;
+ gd->env_valid = 1;
+ }
+ else if (! crc1_ok && crc2_ok)
+ {
+ gd->env_addr = addr2;
+ gd->env_valid = 1;
+ }
+ else if (! crc1_ok && ! crc2_ok)
+ {
+ gd->env_addr = addr_default;
+ gd->env_valid = 0;
+ }
+ else if (flag1 == active_flag && flag2 == obsolete_flag)
+ {
+ gd->env_addr = addr1;
+ gd->env_valid = 1;
+ }
+ else if (flag1 == obsolete_flag && flag2 == active_flag)
+ {
+ gd->env_addr = addr2;
+ gd->env_valid = 1;
+ }
+ else if (flag1 == flag2)
+ {
+ gd->env_addr = addr1;
+ gd->env_valid = 2;
+ }
+ else if (flag1 == 0xFF)
+ {
+ gd->env_addr = addr1;
+ gd->env_valid = 2;
+ }
+ else if (flag2 == 0xFF)
+ {
+ gd->env_addr = addr2;
+ gd->env_valid = 2;
+ }
+
+ return (0);
+}
+
+#ifdef CMD_SAVEENV
+int saveenv(void)
+{
+ int rc = 1;
+
+ if (flash_sect_protect (0, (ulong)flash_addr, end_addr))
+ {
+ goto Done;
+ }
+
+ if (flash_sect_protect (0, (ulong)flash_addr_new, end_addr_new))
+ {
+ goto Done;
+ }
+
+ puts ("Erasing Flash...");
+ if (flash_sect_erase ((ulong)flash_addr_new, end_addr_new))
+ {
+ goto Done;
+ }
+
+ puts ("Writing to Flash... ");
+ if (flash_write(env_ptr->data,
+ (ulong)&(flash_addr_new->data),
+ sizeof(env_ptr->data)) ||
+
+ flash_write((char *)&(env_ptr->crc),
+ (ulong)&(flash_addr_new->crc),
+ sizeof(env_ptr->crc)) ||
+
+ flash_write((char *)&obsolete_flag,
+ (ulong)&(flash_addr->flags),
+ sizeof(flash_addr->flags)) ||
+
+ flash_write((char *)&active_flag,
+ (ulong)&(flash_addr_new->flags),
+ sizeof(flash_addr_new->flags)))
+ {
+ flash_perror (rc);
+ goto Done;
+ }
+ puts ("done\n");
+
+ {
+ env_t * etmp = flash_addr;
+ ulong ltmp = end_addr;
+
+ flash_addr = flash_addr_new;
+ flash_addr_new = etmp;
+
+ end_addr = end_addr_new;
+ end_addr_new = ltmp;
+ }
+
+ rc = 0;
+Done:
+
+ /* try to re-protect */
+ (void) flash_sect_protect (1, (ulong)flash_addr, end_addr);
+ (void) flash_sect_protect (1, (ulong)flash_addr_new, end_addr_new);
+
+ return rc;
+}
+#endif /* CMD_SAVEENV */
+
+#else /* ! CFG_ENV_ADDR_REDUND */
+
+int env_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
+ gd->env_addr = (ulong)&(env_ptr->data);
+ gd->env_valid = 1;
+ } else {
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 0;
+ }
+
+ return (0);
+}
+
+#ifdef CMD_SAVEENV
+
+int saveenv(void)
+{
+ int len, rc;
+ ulong end_addr;
+ ulong flash_sect_addr;
+#if defined(CFG_ENV_SECT_SIZE) && (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE)
+ ulong flash_offset;
+ uchar env_buffer[CFG_ENV_SECT_SIZE];
+#else
+ uchar *env_buffer = (char *)env_ptr;
+#endif /* CFG_ENV_SECT_SIZE */
+ int rcode = 0;
+
+#if defined(CFG_ENV_SECT_SIZE) && (CFG_ENV_SECT_SIZE > CFG_ENV_SIZE)
+
+ flash_offset = ((ulong)flash_addr) & (CFG_ENV_SECT_SIZE-1);
+ flash_sect_addr = ((ulong)flash_addr) & ~(CFG_ENV_SECT_SIZE-1);
+
+ /* copy old contents to temporary buffer */
+ memcpy (env_buffer, (void *)flash_sect_addr, CFG_ENV_SECT_SIZE);
+
+ /* copy current environment to temporary buffer */
+ memcpy ((uchar *)((unsigned long)env_buffer + flash_offset),
+ env_ptr,
+ CFG_ENV_SIZE);
+
+ len = CFG_ENV_SECT_SIZE;
+#else
+ flash_sect_addr = (ulong)flash_addr;
+ len = CFG_ENV_SIZE;
+#endif /* CFG_ENV_SECT_SIZE */
+
+#ifndef CONFIG_INFERNO
+ end_addr = flash_sect_addr + len - 1;
+#else
+ /* this is the last sector, and the size is hardcoded here */
+ /* otherwise we will get stack problems on loading 128 KB environment */
+ end_addr = flash_sect_addr + 0x20000 - 1;
+#endif
+
+ if (flash_sect_protect (0, flash_sect_addr, end_addr))
+ return 1;
+
+ puts ("Erasing Flash...");
+ if (flash_sect_erase (flash_sect_addr, end_addr))
+ return 1;
+
+ puts ("Writing to Flash... ");
+ rc = flash_write(env_buffer, flash_sect_addr, len);
+ if (rc != 0) {
+ flash_perror (rc);
+ rcode = 1;
+ } else {
+ puts ("done\n");
+ }
+
+ /* try to re-protect */
+ (void) flash_sect_protect (1, flash_sect_addr, end_addr);
+ return rcode;
+}
+
+#endif /* CMD_SAVEENV */
+
+#endif /* CFG_ENV_ADDR_REDUND */
+
+void env_relocate_spec (void)
+{
+#if !defined(ENV_IS_EMBEDDED) || defined(CFG_ENV_ADDR_REDUND)
+#ifdef CFG_ENV_ADDR_REDUND
+ DECLARE_GLOBAL_DATA_PTR;
+
+ if (gd->env_addr != (ulong)&(flash_addr->data))
+ {
+ env_t * etmp = flash_addr;
+ ulong ltmp = end_addr;
+
+ flash_addr = flash_addr_new;
+ flash_addr_new = etmp;
+
+ end_addr = end_addr_new;
+ end_addr_new = ltmp;
+ }
+
+ if (flash_addr_new->flags != obsolete_flag &&
+ crc32(0, flash_addr_new->data, ENV_SIZE) ==
+ flash_addr_new->crc)
+ {
+ gd->env_valid = 2;
+ flash_sect_protect (0, (ulong)flash_addr_new, end_addr_new);
+ flash_write((char *)&obsolete_flag,
+ (ulong)&(flash_addr_new->flags),
+ sizeof(flash_addr_new->flags));
+ flash_sect_protect (1, (ulong)flash_addr_new, end_addr_new);
+ }
+
+ if (flash_addr->flags != active_flag &&
+ (flash_addr->flags & active_flag) == active_flag)
+ {
+ gd->env_valid = 2;
+ flash_sect_protect (0, (ulong)flash_addr, end_addr);
+ flash_write((char *)&active_flag,
+ (ulong)&(flash_addr->flags),
+ sizeof(flash_addr->flags));
+ flash_sect_protect (1, (ulong)flash_addr, end_addr);
+ }
+
+ if (gd->env_valid == 2)
+ puts ("*** Warning - some problems detected "
+ "reading environment; recovered successfully\n\n");
+#endif /* CFG_ENV_ADDR_REDUND */
+ memcpy (env_ptr, (void*)flash_addr, CFG_ENV_SIZE);
+#endif /* ! ENV_IS_EMBEDDED || CFG_ENV_ADDR_REDUND */
+}
+
+#endif /* CFG_ENV_IS_IN_FLASH) */
--- /dev/null
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#if defined(CFG_ENV_IS_NOWHERE) /* Environment is nowhere */
+
+#include <command.h>
+#include <environment.h>
+#include <linux/stddef.h>
+#include <malloc.h>
+
+env_t *env_ptr = NULL;
+
+extern uchar default_environment[];
+extern int default_environment_size;
+
+
+void env_relocate_spec (void)
+{
+}
+
+uchar env_get_char_spec (int index)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ return ( *((uchar *)(gd->env_addr + index)) );
+}
+
+/************************************************************************
+ * Initialize Environment use
+ *
+ * We are still running from ROM, so data use is limited
+ */
+int env_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 0;
+
+ return (0);
+}
+
+#endif /* CFG_ENV_IS_NOWHERE) */
--- /dev/null
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * 09-18-2001 Andreas Heppel, Sysgo RTS GmbH <aheppel@sysgo.de>
+ *
+ * It might not be possible in all cases to use 'memcpy()' to copy
+ * the environment to NVRAM, as the NVRAM might not be mapped into
+ * the memory space. (I.e. this is the case for the BAB750). In those
+ * cases it might be possible to access the NVRAM using a different
+ * method. For example, the RTC on the BAB750 is accessible in IO
+ * space using its address and data registers. To enable usage of
+ * NVRAM in those cases I invented the functions 'nvram_read()' and
+ * 'nvram_write()', which will be activated upon the configuration
+ * #define CFG_NVRAM_ACCESS_ROUTINE. Note, that those functions are
+ * strongly dependent on the used HW, and must be redefined for each
+ * board that wants to use them.
+ */
+
+#include <common.h>
+
+#ifdef CFG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */
+
+#include <command.h>
+#include <environment.h>
+#include <cmd_nvedit.h>
+#include <linux/stddef.h>
+#include <malloc.h>
+
+#ifdef CFG_NVRAM_ACCESS_ROUTINE
+extern void *nvram_read(void *dest, const long src, size_t count);
+extern void nvram_write(long dest, const void *src, size_t count);
+env_t *env_ptr = NULL;
+#else
+env_t *env_ptr = (env_t *)CFG_ENV_ADDR;
+#endif
+
+char * env_name_spec = "NVRAM";
+
+extern uchar default_environment[];
+extern int default_environment_size;
+
+extern uchar (*env_get_char)(int);
+extern uchar env_get_char_memory (int index);
+
+
+uchar env_get_char_spec (int index)
+{
+#ifdef CFG_NVRAM_ACCESS_ROUTINE
+ uchar c;
+
+ nvram_read(&c, CFG_ENV_ADDR+index, 1);
+
+ return c;
+#else
+ DECLARE_GLOBAL_DATA_PTR;
+
+ return *((uchar *)(gd->env_addr + index));
+#endif
+}
+
+void env_relocate_spec (void)
+{
+#if defined(CFG_NVRAM_ACCESS_ROUTINE)
+ nvram_read(env_ptr, CFG_ENV_ADDR, CFG_ENV_SIZE);
+#else
+ memcpy (env_ptr, (void*)CFG_ENV_ADDR, CFG_ENV_SIZE);
+#endif
+}
+
+int saveenv (void)
+{
+ int rcode = 0;
+
+#ifdef CFG_NVRAM_ACCESS_ROUTINE
+ nvram_write(CFG_ENV_ADDR, env_ptr, CFG_ENV_SIZE);
+#else
+ if (memcpy ((char *)CFG_ENV_ADDR, env_ptr, CFG_ENV_SIZE) == NULL)
+ rcode = 1 ;
+#endif
+ return rcode;
+}
+
+
+/************************************************************************
+ * Initialize Environment use
+ *
+ * We are still running from ROM, so data use is limited
+ */
+int env_init (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CFG_NVRAM_ACCESS_ROUTINE)
+ ulong crc;
+ uchar data[ENV_SIZE];
+ nvram_read (&crc, CFG_ENV_ADDR, sizeof(ulong));
+ nvram_read (data, CFG_ENV_ADDR+sizeof(ulong), ENV_SIZE);
+
+ if (crc32(0, data, ENV_SIZE) == crc) {
+ gd->env_addr = (ulong)CFG_ENV_ADDR + sizeof(long);
+#else
+ if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
+ gd->env_addr = (ulong)&(env_ptr->data);
+#endif
+ gd->env_valid = 1;
+ } else {
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 0;
+ }
+
+ return (0);
+}
+
+#endif /* CFG_ENV_IS_IN_NVRAM */
*/
#include <config.h>
+#include <environment.h>
/*
* Handle HOSTS that have prepended
# define SYM_CHAR
#endif
-/*
- * Check environment configuration and
- * setup the various values if necessary.
- */
-#if defined(CFG_ENV_IS_IN_FLASH)
-# ifndef CFG_ENV_ADDR
-# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
-# endif
-# ifndef CFG_ENV_OFFSET
-# define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
-# endif
-# ifndef CFG_ENV_SIZE
-# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
-# endif
-# if ((CFG_ENV_ADDR >= CFG_MONITOR_BASE) && \
- ((CFG_ENV_ADDR+CFG_ENV_SIZE) <= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)))
-# define ENV_IS_EMBEDDED
-# endif
-#endif /* CFG_ENV_IS_IN_FLASH */
-
/*
* Generate embedded environment table
* inside ppcboot image, if needed.
#if (defined(CONFIG_FADS) || \
defined(CONFIG_HYMOD) || \
defined(CONFIG_ICU862) || \
- defined(CONFIG_R360MPI) ) && \
+ defined(CONFIG_R360MPI)|| \
+ defined(CONFIG_TQM8xxL) ) && \
defined(ENV_CRC) /* Environment embedded in ppcboot .ppcenv section */
/* XXX - This only works with GNU C */
# define __PPCENV__ __attribute__ ((section(".ppcenv")))
# define ENV_CRC ~0
#endif
-/*
- * Environment table. This will end up
- * in one of a .ppcenv, .text, or .data section
- * depending on board or host configuration.
- *
- * XXX - This only works with GNU C.
- */
-typedef struct environment_s {
- unsigned long crc;
- unsigned char data[CFG_ENV_SIZE - (sizeof(unsigned long))];
-} env_t __attribute__ ((packed));
-
env_t environment __PPCENV__ = {
- ENV_CRC,
+ ENV_CRC, /* CRC Sum */
+ 1, /* Flags: valid */
{
#if defined(CONFIG_BOOTARGS)
"bootargs=" CONFIG_BOOTARGS "\0"
"\0" /* Term. env_t.data with 2 NULLs */
}
};
+#ifdef CFG_ENV_ADDR_REDUND
+env_t redundand_environment __PPCENV__ = {
+ 0, /* CRC Sum: invalid */
+ 0, /* Flags: invalid */
+ {
+ "\0"
+ }
+};
+#endif /* CFG_ENV_ADDR_REDUND */
/*
* These will end up in the .text section
#define CFG_CMD_SDRAM 0x0000004000000000 /* SDRAM DIMM SPD info printout */
#define CFG_CMD_DIAG 0x0000008000000000 /* Diagnostics */
#define CFG_CMD_FPGA 0x0000010000000000 /* FPGA configuration Support */
-#define CFG_CMD_HWFLOW 0x0000002000000000 /* RTS/CTS hw flow control */
+#define CFG_CMD_HWFLOW 0x0000020000000000 /* RTS/CTS hw flow control */
#define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFF /* ALL commands */
#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+
/*
* Miscellaneous configurable options
*/
#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CFG_EBC_PB0AP 0x92015480
+#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (CAN0, 1, 2, 3) initialization */
+#define CFG_EBC_PB1AP 0x01000380 /* enable Ready, BEM=0 */
+#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 2 (Expension Bus) initialization */
+#define CFG_EBC_PB2AP 0x01000280 /* disable Ready, BEM=0 */
+#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 3 (16552) initialization */
+#define CFG_EBC_PB3AP 0x01000380 /* enable Ready, BEM=0 */
+#define CFG_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 4 (FPGA regs) initialization */
+#define CFG_EBC_PB4AP 0x01005380 /* enable Ready, BEM=0 */
+#define CFG_EBC_PB4CR 0xF031C000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
+
+/* Memory Bank 5 (Flash Bank 1/DUMMY) initialization */
+#define CFG_EBC_PB5AP 0x92015480
+#define CFG_EBC_PB5CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in RAM)
*/
#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+
/*
* Miscellaneous configurable options
*/
#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CFG_EBC_PB0AP 0x92015480
+#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (CAN/USB) initialization */
+#define CFG_EBC_PB1AP 0x010053C0 /* enable Ready, BEM=1 */
+#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 2 (Misc-IO/LEDs) initialization */
+#define CFG_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */
+#define CFG_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 3 (CAN Features) initialization */
+#define CFG_EBC_PB3AP 0x80000040 /* no Ready, BEM=1 */
+#define CFG_EBC_PB3CR 0xF021C000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */
+
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in RAM)
*/
#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+
/*
* Miscellaneous configurable options
*/
#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CFG_EBC_PB0AP 0x92015480
+#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Uart 8bit) initialization */
+#define CFG_EBC_PB1AP 0x01000480 /* TWT=2,TH=2,no Ready,BEM=0,SOR=1 */
+#define CFG_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 2 (Uart 32bit) initialization */
+#define CFG_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */
+#define CFG_EBC_PB2CR 0xF011C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR 0xF0000500
+/* Memory Bank 3 (FPGA Reset) initialization */
+#define CFG_EBC_PB3AP 0x010004C0 /* no Ready, BEM=1 */
+#define CFG_EBC_PB3CR 0xF021A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in DPRAM)
#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+
/*
* Miscellaneous configurable options
*/
#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CFG_EBC_PB0AP 0x92015480
+#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization */
+#define CFG_EBC_PB1AP 0x92015480
+#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (PLD - FPGA-boot) initialization */
+#define CFG_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+ /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 3 (PLD - OSL) initialization */
+#define CFG_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+ /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 4 (Spartan2 1) initialization */
+#define CFG_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+ /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
+
+/* Memory Bank 5 (Spartan2 2) initialization */
+#define CFG_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+ /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
+
+/* Memory Bank 6 (Virtex 1) initialization */
+#define CFG_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+ /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 7 (Virtex 2) initialization */
+#define CFG_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+ /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
+
#define CFG_ETHERNET_MAC_ADDR 0x00000000 /* Pass Ethernet MAC to VxWorks */
#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+
/*
* Miscellaneous configurable options
*/
#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
+/*-----------------------------------------------------------------------
+ * External Bus Controller (EBC) Setup
+ */
+
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CFG_EBC_PB0AP 0x92015480
+#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 1 (Flash Bank 1) initialization */
+#define CFG_EBC_PB1AP 0x92015480
+#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
+
+/* Memory Bank 2 (PLD - FPGA-boot) initialization */
+#define CFG_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+ /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 3 (PLD - OSL) initialization */
+#define CFG_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+ /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
+
+/* Memory Bank 4 (Spartan2 1) initialization */
+#define CFG_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+ /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
+
+/* Memory Bank 5 (Spartan2 2) initialization */
+#define CFG_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+ /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
+
+/* Memory Bank 6 (Virtex 1) initialization */
+#define CFG_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+ /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
+
+/* Memory Bank 7 (Virtex 2) initialization */
+#define CFG_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
+ /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
+#define CFG_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
+
#define CFG_ETHERNET_MAC_ADDR 0x00000000 /* Pass Ethernet MAC to VxWorks */
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
+/* Address and size of Redundant Environment Sector */
+#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x00040000) /* Addr of Environment Sector */
+
+#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector */
#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
+#define CFG_ENV_ADDR_REDUND (PHYS_FLASH_1 + 0x80000) /* Addr of Redundant Environment Sector */
+#define CFG_ENV_SIZE_REDUND 0x20000 /* Total Size of Environment Sector */
+
#endif /* __CONFIG_H */
# ifndef CFG_ENV_ADDR
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
# endif
+# if !defined(CFG_ENV_ADDR_REDUND) && defined(CFG_ENV_OFFSET_REDUND)
+# define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + CFG_ENV_OFFSET_REDUND)
+# endif
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
+# if defined(CFG_ENV_ADDR_REDUND) && !defined(CFG_ENV_SIZE_REDUND)
+# define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
+# endif
# if (CFG_ENV_ADDR >= CFG_MONITOR_BASE) && \
(CFG_ENV_ADDR+CFG_ENV_SIZE) <= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
# define ENV_IS_EMBEDDED
# endif
#endif /* CFG_ENV_IS_IN_FLASH */
-#define ENV_SIZE (CFG_ENV_SIZE - sizeof(long))
+#define ENV_SIZE (CFG_ENV_SIZE - sizeof(unsigned long) - 1)
typedef struct environment_s {
- ulong crc; /* CRC32 over data bytes */
- uchar data[CFG_ENV_SIZE - sizeof(ulong)];
+ unsigned long crc; /* CRC32 over data bytes */
+ unsigned char flags; /* active/obsolete flags */
+ unsigned char data[ENV_SIZE]; /* Environment data */
} env_t;
#endif /* _ENVIRONMENT_H_ */
#ifdef ENV_IS_EMBEDDED
int crc ;
unsigned char *envptr = &environment,
- *dataptr = envptr + sizeof(unsigned int);
+ *dataptr = envptr + sizeof(unsigned int) + 1;
unsigned int datasize = env_size - (dataptr - envptr) ;
projects / users / rw / ppcboot.git / commitdiff