Replace disable_kq parameter with user_queue parameter.
The parameter has the following logic:
 -1 = auto (ASIC specific default)
  0 = user queues disabled
  1 = user queues enabled and kernel queues enabled (if supported)
  2 = user queues enabled and kernel queues disabled
The default behavior (-1) is currently the same as 0 for current
ASICs.  To enable user queues (in addition to kernel queues) set
user_queue=1. To enable user queues and disable kernel queues
(to make all resources available to user queues), set user_queue=2.
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 extern int amdgpu_rebar;
 
 extern int amdgpu_wbrf;
-extern int amdgpu_disable_kq;
+extern int amdgpu_user_queue;
 
 #define AMDGPU_VM_MAX_NUM_CTX                  4096
 #define AMDGPU_SG_THRESHOLD                    (256*1024*1024)
 
 int amdgpu_damage_clips = -1; /* auto */
 int amdgpu_umsch_mm_fwlog;
 int amdgpu_rebar = -1; /* auto */
-int amdgpu_disable_kq = -1;
+int amdgpu_user_queue = -1;
 
 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
                        "DRM_UT_CORE",
 module_param_named(rebar, amdgpu_rebar, int, 0444);
 
 /**
- * DOC: disable_kq (int)
- * Disable kernel queues on systems that support user queues.
- * (0 = kernel queues enabled, 1 = kernel queues disabled, -1 = auto (default setting))
+ * DOC: user_queue (int)
+ * Enable user queues on systems that support user queues.
+ * -1 = auto (ASIC specific default)
+ *  0 = user queues disabled
+ *  1 = user queues enabled and kernel queues enabled (if supported)
+ *  2 = user queues enabled and kernel queues disabled
  */
-MODULE_PARM_DESC(disable_kq, "Disable kernel queues (-1 = auto (default), 0 = enable KQ, 1 = disable KQ)");
-module_param_named(disable_kq, amdgpu_disable_kq, int, 0444);
+MODULE_PARM_DESC(user_queue, "Enable user queues (-1 = auto (default), 0 = disable, 1 = enable, 2 = enable UQs and disable KQs)");
+module_param_named(user_queue, amdgpu_user_queue, int, 0444);
 
 /* These devices are not supported by amdgpu.
  * They are supported by the mach64, r128, radeon drivers
 
        struct mutex                    workload_profile_mutex;
 
        bool                            disable_kq;
+       bool                            disable_uq;
 };
 
 struct amdgpu_gfx_ras_reg_entry {
 
        uint32_t                supported_reset;
        struct list_head        reset_callback_list;
        bool                    no_user_submission;
+       bool                    disable_uq;
 };
 
 /*
 
        case IP_VERSION(11, 0, 3):
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
                /* add firmware version checks here */
-               if (0) {
+               if (0 && !adev->gfx.disable_uq) {
                        adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
                        adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
                }
        case IP_VERSION(11, 5, 3):
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
                /* add firmware version checks here */
-               if (0) {
+               if (0 && !adev->gfx.disable_uq) {
                        adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
                        adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
                }
 {
        struct amdgpu_device *adev = ip_block->adev;
 
-       if (amdgpu_disable_kq == 1)
+       switch (amdgpu_user_queue) {
+       case -1:
+       case 0:
+       default:
+               adev->gfx.disable_kq = false;
+               adev->gfx.disable_uq = true;
+               break;
+       case 1:
+               adev->gfx.disable_kq = false;
+               adev->gfx.disable_uq = false;
+               break;
+       case 2:
                adev->gfx.disable_kq = true;
+               adev->gfx.disable_uq = false;
+               break;
+       }
 
        adev->gfx.funcs = &gfx_v11_0_gfx_funcs;
 
 
        case IP_VERSION(12, 0, 1):
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
                /* add firmware version checks here */
-               if (0) {
+               if (0 && !adev->gfx.disable_uq) {
                        adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
                        adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
                }
 {
        struct amdgpu_device *adev = ip_block->adev;
 
-       if (amdgpu_disable_kq == 1)
+       switch (amdgpu_user_queue) {
+       case -1:
+       case 0:
+       default:
+               adev->gfx.disable_kq = false;
+               adev->gfx.disable_uq = true;
+               break;
+       case 1:
+               adev->gfx.disable_kq = false;
+               adev->gfx.disable_uq = false;
+               break;
+       case 2:
                adev->gfx.disable_kq = true;
+               adev->gfx.disable_uq = false;
+               break;
+       }
 
        adev->gfx.funcs = &gfx_v12_0_gfx_funcs;
 
 
        struct amdgpu_device *adev = ip_block->adev;
        int r;
 
-       if (amdgpu_disable_kq == 1)
+       switch (amdgpu_user_queue) {
+       case -1:
+       case 0:
+       default:
+               adev->sdma.no_user_submission = false;
+               adev->sdma.disable_uq = true;
+               break;
+       case 1:
+               adev->sdma.no_user_submission = false;
+               adev->sdma.disable_uq = false;
+               break;
+       case 2:
                adev->sdma.no_user_submission = true;
+               adev->sdma.disable_uq = false;
+               break;
+       }
 
        r = amdgpu_sdma_init_microcode(adev, 0, true);
        if (r)
 
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
        /* add firmware version checks here */
-       if (0)
+       if (0 && !adev->sdma.disable_uq)
                adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
 #endif
        r = amdgpu_sdma_sysfs_reset_mask_init(adev);
 
        struct amdgpu_device *adev = ip_block->adev;
        int r;
 
-       if (amdgpu_disable_kq == 1)
+       switch (amdgpu_user_queue) {
+       case -1:
+       case 0:
+       default:
+               adev->sdma.no_user_submission = false;
+               adev->sdma.disable_uq = true;
+               break;
+       case 1:
+               adev->sdma.no_user_submission = false;
+               adev->sdma.disable_uq = false;
+               break;
+       case 2:
                adev->sdma.no_user_submission = true;
+               adev->sdma.disable_uq = false;
+               break;
+       }
 
        r = amdgpu_sdma_init_microcode(adev, 0, true);
        if (r) {
 
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
        /* add firmware version checks here */
-       if (0)
+       if (0 && !adev->sdma.disable_uq)
                adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
 #endif