crypto: qat - fix crypto capability detection for 4xxx

When extending the capability detection logic for 4xxx devices the
SMx algorithms were accidentally missed.
Enable these SMx capabilities by default for QAT GEN4 devices.

Check for device variants where the SMx algorithms are explicitly
disabled by the GEN4 hardware. This is indicated in fusectl1
register.
Mask out SM3 and SM4 based on a bit specific to those algorithms.
Mask out SM2 if the PKE slice is not present.

Fixes: 4b44d28c715d ("crypto: qat - extend crypto capability detection for 4xxx")
Signed-off-by: Adam Guerin <adam.guerin@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: Fiona Trahe <fiona.trahe@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c b/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
index 268a1f7694fcd84d8407d954fcb855a3487da9a6..dd4464b7e00b18763f02b06ea90560a447fb739d 100644 (file)
--- a/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
+++ b/drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
@@ -225,6 +225,8 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
                          ICP_ACCEL_CAPABILITIES_HKDF |
                          ICP_ACCEL_CAPABILITIES_CHACHA_POLY |
                          ICP_ACCEL_CAPABILITIES_AESGCM_SPC |
+                         ICP_ACCEL_CAPABILITIES_SM3 |
+                         ICP_ACCEL_CAPABILITIES_SM4 |
                          ICP_ACCEL_CAPABILITIES_AES_V2;
 
        /* A set bit in fusectl1 means the feature is OFF in this SKU */
@@ -248,12 +250,19 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev)
                capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
        }
 
+       if (fusectl1 & ICP_ACCEL_4XXX_MASK_SMX_SLICE) {
+               capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SM3;
+               capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SM4;
+       }
+
        capabilities_asym = ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
                          ICP_ACCEL_CAPABILITIES_CIPHER |
+                         ICP_ACCEL_CAPABILITIES_SM2 |
                          ICP_ACCEL_CAPABILITIES_ECEDMONT;
 
        if (fusectl1 & ICP_ACCEL_4XXX_MASK_PKE_SLICE) {
                capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
+               capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_SM2;
                capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;
        }
 

diff --git a/drivers/crypto/intel/qat/qat_common/icp_qat_hw.h b/drivers/crypto/intel/qat/qat_common/icp_qat_hw.h
index a65059e56248ab162c98ff170964ebc8daf809d3..0c8883e2ccc6dc1979ac32811b2c72de38a27a3e 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/icp_qat_hw.h
+++ b/drivers/crypto/intel/qat/qat_common/icp_qat_hw.h
@@ -97,7 +97,10 @@ enum icp_qat_capabilities_mask {
        ICP_ACCEL_CAPABILITIES_SHA3_EXT = BIT(15),
        ICP_ACCEL_CAPABILITIES_AESGCM_SPC = BIT(16),
        ICP_ACCEL_CAPABILITIES_CHACHA_POLY = BIT(17),
-       /* Bits 18-21 are currently reserved */
+       ICP_ACCEL_CAPABILITIES_SM2 = BIT(18),
+       ICP_ACCEL_CAPABILITIES_SM3 = BIT(19),
+       ICP_ACCEL_CAPABILITIES_SM4 = BIT(20),
+       /* Bit 21 is currently reserved */
        ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY = BIT(22),
        ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64 = BIT(23),
        ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION = BIT(24),