]> www.infradead.org Git - users/jedix/linux-maple.git/commitdiff
PCI: pciehp: wait 1000 ms before Link Training check
authorKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Thu, 10 Nov 2011 07:40:37 +0000 (16:40 +0900)
committerZhenzhong Duan <zhenzhong.duan@oracle.com>
Mon, 11 Jun 2012 02:32:16 +0000 (10:32 +0800)
Orabug:13993738
We need to wait for 1000 ms after Data Link Layer Link Active (DLLLA)
bit reads 1b before sending configuration request. Currently pciehp
does this wait after checking Link Training (LT) bit. But we need it
before checking LT bit because LT is still set even after DLLLA bit is
set on some platforms.

Acked-by: Yinghai Lu <yinghai@kernel.org>
Tested-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
(cherry picked from commit 0027cb3e1947d0f453fece40ed16764fb362bac6)

Signed-off-by: Zhenzhong Duan <zhenzhong.duan@oracle.com>
drivers/pci/hotplug/pciehp_hpc.c

index 50a23da5d24dc5ea248e34c73c6f13855f538983..1e4a954564953244ac48941d591045352f81e97d 100644 (file)
@@ -287,6 +287,14 @@ int pciehp_check_link_status(struct controller *ctrl)
         } else
                 msleep(1000);
 
+       /*
+        * Need to wait for 1000 ms after Data Link Layer Link Active
+        * (DLLLA) bit reads 1b before sending configuration request.
+        * We need it before checking Link Training (LT) bit becuase
+        * LT is still set even after DLLLA bit is set on some platform.
+        */
+       msleep(1000);
+
        retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
        if (retval) {
                ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");