arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board

SCIF1 interface is available on PMOD1 connector (CN7) on carrier board.

This patch adds pinmux and scif1 node to carrier board dtsi file for
RZ/G2LC SMARC EVK.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220203170636.7747-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
index 1032f6563515718750aa0e62b4ed8b358e6049a5..ec9e08ec082248db51c975f2c245fe78b0b40e94 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -17,6 +17,13 @@
                         <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
        };
 
+       scif1_pins: scif1 {
+               pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
+                        <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
+                        <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
+                        <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
+       };
+
        sd1-pwr-en-hog {
                gpio-hog;
                gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;

diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
index ca5ca7ce66922419d4f79a5a1f6b6bc13e17754c..1b59ef3762965c6c0924bd9ad82c5781abe0281f 100644 (file)
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
@@ -34,3 +34,29 @@
 #include "rzg2lc-smarc-som.dtsi"
 #include "rzg2lc-smarc-pinfunction.dtsi"
 #include "rz-smarc-common.dtsi"
+
+/* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */
+#define PMOD1_SER0     1
+
+/ {
+       aliases {
+               serial1 = &scif1;
+       };
+};
+
+/*
+ * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
+ * SW1 should be at position 2->3 so that SER0_CTS# line is activated
+ * SW2 should be at position 2->3 so that SER0_TX line is activated
+ * SW3 should be at position 2->3 so that SER0_RX line is activated
+ * SW4 should be at position 2->3 so that SER0_RTS# line is activated
+ */
+#if (!SW_SCIF_CAN && PMOD1_SER0)
+&scif1 {
+       pinctrl-0 = <&scif1_pins>;
+       pinctrl-names = "default";
+
+       uart-has-rtscts;
+       status = "okay";
+};
+#endif