Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
 # define GEN6_CSUNIT_CLOCK_GATE_DISABLE                        (1 << 7)
 
 #define GEN6_UCGCTL2                           0x9404
+# define GEN6_VFUNIT_CLOCK_GATE_DISABLE                        (1 << 31)
 # define GEN7_VDSUNIT_CLOCK_GATE_DISABLE               (1 << 30)
 # define GEN7_TDLUNIT_CLOCK_GATE_DISABLE               (1 << 22)
 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE               (1 << 13)
 
                I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
                           GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
                           GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
+
+               /* WaDisableVFUnitClockGating:skl */
+               I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
+                          GEN6_VFUNIT_CLOCK_GATE_DISABLE);
        }
 
        if (INTEL_REVID(dev) <= SKL_REVID_D0) {