clk: samsung: fix getting Exynos4 fin_pll rate from external clocks

Commit 0dc83ad8bfc9 ("clk: samsung: Don't register clkdev lookup for the
fixed rate clocks") claimed registering clkdev lookup is not necessary
anymore, but that was not entirely true: Exynos4210/4212/4412 clock code
still relied on it to get the clock rate of xxti or xusbxti external
clocks.

Drop that requirement by accessing already registered clk_hw when
looking up the xxti/xusbxti rate.

Reported-by: Artur Weber <aweber.kernel@gmail.com>
Closes: https://lore.kernel.org/all/6227c1fb-d769-462a-b79b-abcc15d3db8e@gmail.com/
Fixes: 0dc83ad8bfc9 ("clk: samsung: Don't register clkdev lookup for the fixed rate clocks")
Cc: <stable@vger.kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240722063309.60054-1-krzysztof.kozlowski@linaro.org
Tested-by: Artur Weber <aweber.kernel@gmail.com> # Exynos4212
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index a026ccca7315f1c403daa9e1201c8536e8a83ae7..28945b6b0ee1c1e3908349fa9f071d3845057eaf 100644 (file)
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -1040,19 +1040,20 @@ static unsigned long __init exynos4_get_xom(void)
 static void __init exynos4_clk_register_finpll(struct samsung_clk_provider *ctx)
 {
        struct samsung_fixed_rate_clock fclk;
-       struct clk *clk;
-       unsigned long finpll_f = 24000000;
+       unsigned long finpll_f;
+       unsigned int parent;
        char *parent_name;
        unsigned int xom = exynos4_get_xom();
 
        parent_name = xom & 1 ? "xusbxti" : "xxti";
-       clk = clk_get(NULL, parent_name);
-       if (IS_ERR(clk)) {
+       parent = xom & 1 ? CLK_XUSBXTI : CLK_XXTI;
+
+       finpll_f = clk_hw_get_rate(ctx->clk_data.hws[parent]);
+       if (!finpll_f) {
                pr_err("%s: failed to lookup parent clock %s, assuming "
                        "fin_pll clock frequency is 24MHz\n", __func__,
                        parent_name);
-       } else {
-               finpll_f = clk_get_rate(clk);
+               finpll_f = 24000000;
        }
 
        fclk.id = CLK_FIN_PLL;