EDAC/amd64: Remove unused register accesses

A number of UMC registers are read only for the purpose of debug printing. They
are not used in any calculations. Nor do they have any specific debug value.

Remove them.

Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20240606-fix-smn-bad-read-v4-1-ffde21931c3f@amd.com

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index a17f3c0cdfa601676ac8498293d60645d63b9655..dfc4fb8f7a7a4c13b35abfd04b679257255ad84c 100644 (file)
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -20,7 +20,6 @@ static inline u32 get_umc_reg(struct amd64_pvt *pvt, u32 reg)
                return reg;
 
        switch (reg) {
-       case UMCCH_ADDR_CFG:            return UMCCH_ADDR_CFG_DDR5;
        case UMCCH_ADDR_MASK_SEC:       return UMCCH_ADDR_MASK_SEC_DDR5;
        case UMCCH_DIMM_CFG:            return UMCCH_DIMM_CFG_DDR5;
        }
@@ -1341,22 +1340,15 @@ static void umc_debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
 static void umc_dump_misc_regs(struct amd64_pvt *pvt)
 {
        struct amd64_umc *umc;
-       u32 i, tmp, umc_base;
+       u32 i;
 
        for_each_umc(i) {
-               umc_base = get_umc_base(i);
                umc = &pvt->umc[i];
 
                edac_dbg(1, "UMC%d DIMM cfg: 0x%x\n", i, umc->dimm_cfg);
                edac_dbg(1, "UMC%d UMC cfg: 0x%x\n", i, umc->umc_cfg);
                edac_dbg(1, "UMC%d SDP ctrl: 0x%x\n", i, umc->sdp_ctrl);
                edac_dbg(1, "UMC%d ECC ctrl: 0x%x\n", i, umc->ecc_ctrl);
-
-               amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ECC_BAD_SYMBOL, &tmp);
-               edac_dbg(1, "UMC%d ECC bad symbol: 0x%x\n", i, tmp);
-
-               amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_UMC_CAP, &tmp);
-               edac_dbg(1, "UMC%d UMC cap: 0x%x\n", i, tmp);
                edac_dbg(1, "UMC%d UMC cap high: 0x%x\n", i, umc->umc_cap_hi);
 
                edac_dbg(1, "UMC%d ECC capable: %s, ChipKill ECC capable: %s\n",
@@ -1369,14 +1361,6 @@ static void umc_dump_misc_regs(struct amd64_pvt *pvt)
                edac_dbg(1, "UMC%d x16 DIMMs present: %s\n",
                                i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no");
 
-               if (umc->dram_type == MEM_LRDDR4 || umc->dram_type == MEM_LRDDR5) {
-                       amd_smn_read(pvt->mc_node_id,
-                                    umc_base + get_umc_reg(pvt, UMCCH_ADDR_CFG),
-                                    &tmp);
-                       edac_dbg(1, "UMC%d LRDIMM %dx rank multiply\n",
-                                       i, 1 << ((tmp >> 4) & 0x3));
-               }
-
                umc_debug_display_dimm_sizes(pvt, i);
        }
 }

diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index b879b12971e7bd5c642b5e8ced4033086e9d69c7..17228d07de4c8c780f5ef2d10fdc0e051a1818f2 100644 (file)
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -256,15 +256,11 @@
 #define UMCCH_ADDR_MASK                        0x20
 #define UMCCH_ADDR_MASK_SEC            0x28
 #define UMCCH_ADDR_MASK_SEC_DDR5       0x30
-#define UMCCH_ADDR_CFG                 0x30
-#define UMCCH_ADDR_CFG_DDR5            0x40
 #define UMCCH_DIMM_CFG                 0x80
 #define UMCCH_DIMM_CFG_DDR5            0x90
 #define UMCCH_UMC_CFG                  0x100
 #define UMCCH_SDP_CTRL                 0x104
 #define UMCCH_ECC_CTRL                 0x14C
-#define UMCCH_ECC_BAD_SYMBOL           0xD90
-#define UMCCH_UMC_CAP                  0xDF0
 #define UMCCH_UMC_CAP_HI               0xDF4
 
 /* UMC CH bitfields */