drm/amd/display: Fix VRR cannot enable

[Why]
Sometimes the VRR cannot enable after login to the desktop.

User space may call the DRM_IOCTL_MODE_GETCONNECTOR right after
the DRM_IOCTL_MODE_RMFB.

After calling DRM_IOCTL_MODE_RMFB to remove all the frame buffer
and it will cause the driver to disable the crtc and disable the
link while calling the link_set_dpms_off().

It will cause the dpcd read failed in amdgpu_dm_update_freesync_caps()
while try to get the DP_MSA_TIMING_PAR_IGNORED capability and think
the sink side does not support VRR.

[How]
Use the dpcd_caps.allow_invalid_MSA_timing_param flag instead of
reading from dpcd directly.

dpcd_caps.allow_invalid_MSA_timing_param flag is updated during HPD.
It is safe to replace the original method.

Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: Jerry Zuo <jerry.zuo@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 92774a871e982ea72a74e143fe315c57e8f6d04a..a3b0f2748af090559eddee24de68a6ee0181477d 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -11721,25 +11721,6 @@ fail:
        return ret;
 }
 
-static bool is_dp_capable_without_timing_msa(struct dc *dc,
-                                            struct amdgpu_dm_connector *amdgpu_dm_connector)
-{
-       u8 dpcd_data;
-       bool capable = false;
-
-       if (amdgpu_dm_connector->dc_link &&
-               dm_helpers_dp_read_dpcd(
-                               NULL,
-                               amdgpu_dm_connector->dc_link,
-                               DP_DOWN_STREAM_PORT_COUNT,
-                               &dpcd_data,
-                               sizeof(dpcd_data))) {
-               capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false;
-       }
-
-       return capable;
-}
-
 static bool dm_edid_parser_send_cea(struct amdgpu_display_manager *dm,
                unsigned int offset,
                unsigned int total_length,
@@ -12042,8 +12023,8 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector,
                     sink->sink_signal == SIGNAL_TYPE_EDP)) {
                bool edid_check_required = false;
 
-               if (is_dp_capable_without_timing_msa(adev->dm.dc,
-                                                    amdgpu_dm_connector)) {
+               if (amdgpu_dm_connector->dc_link &&
+                   amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) {
                        if (edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) {
                                amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq;
                                amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq;