struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
        struct arm_smmu_device *smmu = smmu_domain->smmu;
        int idx = smmu_domain->cfg.cbndx;
+       int ret;
 
        fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR);
        if (!(fsr & ARM_SMMU_FSR_FAULT))
        iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR);
        cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx));
 
-       dev_err_ratelimited(smmu->dev,
-       "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
+       ret = report_iommu_fault(domain, NULL, iova,
+               fsynr & ARM_SMMU_FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ);
+
+       if (ret == -ENOSYS)
+               dev_err_ratelimited(smmu->dev,
+               "Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d\n",
                            fsr, iova, fsynr, cbfrsynra, idx);
 
        arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr);