net: phy: marvell10g: add all MACTYPE definitions for 88X33x0

Add all MACTYPE definitions for 88X3310, 88X3310P, 88X3340 and 88X3340P.

In order to have consistent naming, rename
MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH to
MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH.

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index 7552a658a513a6072bdc214a6f306481a89e534d..7d9a45437b6974bd398d9461c6946dad36dd506b 100644 (file)
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -78,10 +78,18 @@ enum {
 
        /* Vendor2 MMD registers */
        MV_V2_PORT_CTRL         = 0xf001,
-       MV_V2_PORT_CTRL_PWRDOWN                 = BIT(11),
-       MV_V2_33X0_PORT_CTRL_SWRST              = BIT(15),
-       MV_V2_33X0_PORT_CTRL_MACTYPE_MASK       = 0x7,
-       MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH = 0x6,
+       MV_V2_PORT_CTRL_PWRDOWN                                 = BIT(11),
+       MV_V2_33X0_PORT_CTRL_SWRST                              = BIT(15),
+       MV_V2_33X0_PORT_CTRL_MACTYPE_MASK                       = 0x7,
+       MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI                      = 0x0,
+       MV_V2_3310_PORT_CTRL_MACTYPE_XAUI_RATE_MATCH            = 0x1,
+       MV_V2_3340_PORT_CTRL_MACTYPE_RXAUI_NO_SGMII_AN          = 0x1,
+       MV_V2_33X0_PORT_CTRL_MACTYPE_RXAUI_RATE_MATCH           = 0x2,
+       MV_V2_3310_PORT_CTRL_MACTYPE_XAUI                       = 0x3,
+       MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER                   = 0x4,
+       MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_NO_SGMII_AN       = 0x5,
+       MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH        = 0x6,
+       MV_V2_33X0_PORT_CTRL_MACTYPE_USXGMII                    = 0x7,
        /* Temperature control/read registers (88X3310 only) */
        MV_V2_TEMP_CTRL         = 0xf08a,
        MV_V2_TEMP_CTRL_MASK    = 0xc000,
@@ -480,7 +488,7 @@ static int mv3310_config_init(struct phy_device *phydev)
        if (val < 0)
                return val;
        priv->rate_match = ((val & MV_V2_33X0_PORT_CTRL_MACTYPE_MASK) ==
-                       MV_V2_33X0_PORT_CTRL_MACTYPE_RATE_MATCH);
+                       MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER_RATE_MATCH);
 
        /* Enable EDPD mode - saving 600mW */
        return mv3310_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);