.dma      = { 0x00000001, gf119_dma_new },
        .fifo     = { 0x00000001, gm107_fifo_new },
        .gr       = { 0x00000001, gm107_gr_new },
-       .nvdec[0] = gm107_nvdec_new,
+       .nvdec    = { 0x00000001, gm107_nvdec_new },
        .nvenc[0] = gm107_nvenc_new,
        .sw = gf100_sw_new,
 };
        .dma      = { 0x00000001, gf119_dma_new },
        .fifo     = { 0x00000001, gm200_fifo_new },
        .gr       = { 0x00000001, gm200_gr_new },
-       .nvdec[0] = gm107_nvdec_new,
+       .nvdec    = { 0x00000001, gm107_nvdec_new },
        .nvenc[0] = gm107_nvenc_new,
        .nvenc[1] = gm107_nvenc_new,
        .sw = gf100_sw_new,
        .dma      = { 0x00000001, gf119_dma_new },
        .fifo     = { 0x00000001, gm200_fifo_new },
        .gr       = { 0x00000001, gm200_gr_new },
-       .nvdec[0] = gm107_nvdec_new,
+       .nvdec    = { 0x00000001, gm107_nvdec_new },
        .nvenc[0] = gm107_nvenc_new,
        .nvenc[1] = gm107_nvenc_new,
        .sw = gf100_sw_new,
        .dma      = { 0x00000001, gf119_dma_new },
        .fifo     = { 0x00000001, gm200_fifo_new },
        .gr       = { 0x00000001, gm200_gr_new },
-       .nvdec[0] = gm107_nvdec_new,
+       .nvdec    = { 0x00000001, gm107_nvdec_new },
        .nvenc[0] = gm107_nvenc_new,
        .sw = gf100_sw_new,
 };
        .disp     = { 0x00000001, gp100_disp_new },
        .fifo     = { 0x00000001, gp100_fifo_new },
        .gr       = { 0x00000001, gp100_gr_new },
-       .nvdec[0] = gm107_nvdec_new,
+       .nvdec    = { 0x00000001, gm107_nvdec_new },
        .nvenc[0] = gm107_nvenc_new,
        .nvenc[1] = gm107_nvenc_new,
        .nvenc[2] = gm107_nvenc_new,
        .dma      = { 0x00000001, gf119_dma_new },
        .fifo     = { 0x00000001, gp100_fifo_new },
        .gr       = { 0x00000001, gp102_gr_new },
-       .nvdec[0] = gm107_nvdec_new,
+       .nvdec    = { 0x00000001, gm107_nvdec_new },
        .nvenc[0] = gm107_nvenc_new,
        .nvenc[1] = gm107_nvenc_new,
        .sec2 = gp102_sec2_new,
        .dma      = { 0x00000001, gf119_dma_new },
        .fifo     = { 0x00000001, gp100_fifo_new },
        .gr       = { 0x00000001, gp104_gr_new },
-       .nvdec[0] = gm107_nvdec_new,
+       .nvdec    = { 0x00000001, gm107_nvdec_new },
        .nvenc[0] = gm107_nvenc_new,
        .nvenc[1] = gm107_nvenc_new,
        .sec2 = gp102_sec2_new,
        .dma      = { 0x00000001, gf119_dma_new },
        .fifo     = { 0x00000001, gp100_fifo_new },
        .gr       = { 0x00000001, gp104_gr_new },
-       .nvdec[0] = gm107_nvdec_new,
+       .nvdec    = { 0x00000001, gm107_nvdec_new },
        .nvenc[0] = gm107_nvenc_new,
        .sec2 = gp102_sec2_new,
        .sw = gf100_sw_new,
        .dma      = { 0x00000001, gf119_dma_new },
        .fifo     = { 0x00000001, gp100_fifo_new },
        .gr       = { 0x00000001, gp107_gr_new },
-       .nvdec[0] = gm107_nvdec_new,
+       .nvdec    = { 0x00000001, gm107_nvdec_new },
        .nvenc[0] = gm107_nvenc_new,
        .nvenc[1] = gm107_nvenc_new,
        .sec2 = gp102_sec2_new,
        .dma      = { 0x00000001, gf119_dma_new },
        .fifo     = { 0x00000001, gp100_fifo_new },
        .gr       = { 0x00000001, gp108_gr_new },
-       .nvdec[0] = gm107_nvdec_new,
+       .nvdec    = { 0x00000001, gm107_nvdec_new },
        .sec2 = gp108_sec2_new,
        .sw = gf100_sw_new,
 };
        .dma      = { 0x00000001, gv100_dma_new },
        .fifo     = { 0x00000001, gv100_fifo_new },
        .gr       = { 0x00000001, gv100_gr_new },
-       .nvdec[0] = gm107_nvdec_new,
+       .nvdec    = { 0x00000001, gm107_nvdec_new },
        .nvenc[0] = gm107_nvenc_new,
        .nvenc[1] = gm107_nvenc_new,
        .nvenc[2] = gm107_nvenc_new,
        .dma      = { 0x00000001, gv100_dma_new },
        .fifo     = { 0x00000001, tu102_fifo_new },
        .gr       = { 0x00000001, tu102_gr_new },
-       .nvdec[0] = gm107_nvdec_new,
+       .nvdec    = { 0x00000001, gm107_nvdec_new },
        .nvenc[0] = gm107_nvenc_new,
        .sec2 = tu102_sec2_new,
 };
        .dma      = { 0x00000001, gv100_dma_new },
        .fifo     = { 0x00000001, tu102_fifo_new },
        .gr       = { 0x00000001, tu102_gr_new },
-       .nvdec[0] = gm107_nvdec_new,
-       .nvdec[1] = gm107_nvdec_new,
+       .nvdec    = { 0x00000003, gm107_nvdec_new },
        .nvenc[0] = gm107_nvenc_new,
        .sec2 = tu102_sec2_new,
 };
        .dma      = { 0x00000001, gv100_dma_new },
        .fifo     = { 0x00000001, tu102_fifo_new },
        .gr       = { 0x00000001, tu102_gr_new },
-       .nvdec[0] = gm107_nvdec_new,
-       .nvdec[1] = gm107_nvdec_new,
-       .nvdec[2] = gm107_nvdec_new,
+       .nvdec    = { 0x00000007, gm107_nvdec_new },
        .nvenc[0] = gm107_nvenc_new,
        .sec2 = tu102_sec2_new,
 };
        .dma      = { 0x00000001, gv100_dma_new },
        .fifo     = { 0x00000001, tu102_fifo_new },
        .gr       = { 0x00000001, tu102_gr_new },
-       .nvdec[0] = gm107_nvdec_new,
+       .nvdec    = { 0x00000001, gm107_nvdec_new },
        .nvenc[0] = gm107_nvenc_new,
        .sec2 = tu102_sec2_new,
 };
        .dma      = { 0x00000001, gv100_dma_new },
        .fifo     = { 0x00000001, tu102_fifo_new },
        .gr       = { 0x00000001, tu102_gr_new },
-       .nvdec[0] = gm107_nvdec_new,
+       .nvdec    = { 0x00000001, gm107_nvdec_new },
        .nvenc[0] = gm107_nvenc_new,
        .sec2 = tu102_sec2_new,
 };
                _(NVKM_ENGINE_NVENC0  , nvenc[0]);
                _(NVKM_ENGINE_NVENC1  , nvenc[1]);
                _(NVKM_ENGINE_NVENC2  , nvenc[2]);
-               _(NVKM_ENGINE_NVDEC0  , nvdec[0]);
-               _(NVKM_ENGINE_NVDEC1  , nvdec[1]);
-               _(NVKM_ENGINE_NVDEC2  , nvdec[2]);
                _(NVKM_ENGINE_PM      ,       pm);
                _(NVKM_ENGINE_SEC     ,      sec);
                _(NVKM_ENGINE_SEC2    ,     sec2);
                case NVKM_ENGINE_CE6:
                case NVKM_ENGINE_CE7:
                case NVKM_ENGINE_CE8:
+               case NVKM_ENGINE_NVDEC1:
+               case NVKM_ENGINE_NVDEC2:
                        break;
                default:
                        WARN_ON(1);