rasdaemon: enable IMC status usage for Haswell-E

Enable IMC status bank for Haswell-E, as described in Intel SDM Vol.3C
Table 35-27.

Signed-off-by: Seiichi Ikarashi <s.ikarashi@jp.fujitsu.com>
Signed-off-by: Aristeu Rozanski <aris@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>

diff --git a/mce-intel.c b/mce-intel.c
index 69ea00e8ccbc9cdbc37ff6b469df75c8bcf058fe..368460227eebafd18875e77565c1d6272cd358b8 100644 (file)
--- a/mce-intel.c
+++ b/mce-intel.c
@@ -457,6 +457,7 @@ int set_intel_imc_log(enum cputype cputype, unsigned ncpus)
        switch (cputype) {
        case CPU_SANDY_BRIDGE_EP:
        case CPU_IVY_BRIDGE_EPEX:
+       case CPU_HASWELL_EPEX:
                msr = 0x17f;    /* MSR_ERROR_CONTROL */
                bit = 0x2;      /* MemError Log Enable */
                break;

diff --git a/ras-mce-handler.c b/ras-mce-handler.c
index 63f14fd4dd799e5cbc80e2cebb51779e5d744d7e..fb6db8a12d4309ff77789eb6a4203f7fa3109830 100644 (file)
--- a/ras-mce-handler.c
+++ b/ras-mce-handler.c
@@ -221,6 +221,7 @@ int register_mce_handler(struct ras_events *ras, unsigned ncpus)
        switch (mce->cputype) {
        case CPU_SANDY_BRIDGE_EP:
        case CPU_IVY_BRIDGE_EPEX:
+       case CPU_HASWELL_EPEX:
                set_intel_imc_log(mce->cputype, ncpus);
        default:
                break;