net: phy: realtek: merge the drivers for internal NBase-T PHY's

The Realtek RTL8125/RTL8126 NBase-T MAC/PHY chips have internal PHY's
which are register-compatible, at least for the registers we use here.
So let's use just one PHY driver to support all of them.
These internal PHY's exist also as external C45 PHY's, but on the
internal PHY's no access to MMD registers is possible. This can be
used to differentiate between the internal and external version.

As a side effect the drivers for two now external-only drivers don't
require read_mmd/write_mmd hooks any longer.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Link: https://patch.msgid.link/c57081a6-811f-4571-ab35-34f4ca6de9af@gmail.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>

diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 905038b1bb6414fe6efc65ac9eaee4311c5cb844..666462120531736a03e5411d7ed5fe252fe0f981 100644 (file)
--- a/drivers/net/phy/realtek.c
+++ b/drivers/net/phy/realtek.c
@@ -95,6 +95,7 @@
 
 #define RTL_GENERIC_PHYID                      0x001cc800
 #define RTL_8211FVD_PHYID                      0x001cc878
+#define RTL_8221B                              0x001cc840
 #define RTL_8221B_VB_CG                                0x001cc849
 #define RTL_8221B_VN_CG                                0x001cc84a
 #define RTL_8251B                              0x001cc862
@@ -1077,6 +1078,23 @@ static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
        return val >= 0 && val & MDIO_PMA_SPEED_2_5G;
 }
 
+/* On internal PHY's MMD reads over C22 always return 0.
+ * Check a MMD register which is known to be non-zero.
+ */
+static bool rtlgen_supports_mmd(struct phy_device *phydev)
+{
+       int val;
+
+       phy_lock_mdio_bus(phydev);
+       __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS);
+       __phy_write(phydev, MII_MMD_DATA, MDIO_PCS_EEE_ABLE);
+       __phy_write(phydev, MII_MMD_CTRL, MDIO_MMD_PCS | MII_MMD_CTRL_NOINCR);
+       val = __phy_read(phydev, MII_MMD_DATA);
+       phy_unlock_mdio_bus(phydev);
+
+       return val > 0;
+}
+
 static int rtlgen_match_phy_device(struct phy_device *phydev)
 {
        return phydev->phy_id == RTL_GENERIC_PHYID &&
@@ -1086,7 +1104,8 @@ static int rtlgen_match_phy_device(struct phy_device *phydev)
 static int rtl8226_match_phy_device(struct phy_device *phydev)
 {
        return phydev->phy_id == RTL_GENERIC_PHYID &&
-              rtlgen_supports_2_5gbps(phydev);
+              rtlgen_supports_2_5gbps(phydev) &&
+              rtlgen_supports_mmd(phydev);
 }
 
 static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
@@ -1098,6 +1117,11 @@ static int rtlgen_is_c45_match(struct phy_device *phydev, unsigned int id,
                return !is_c45 && (id == phydev->phy_id);
 }
 
+static int rtl8221b_match_phy_device(struct phy_device *phydev)
+{
+       return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev);
+}
+
 static int rtl8221b_vb_cg_c22_match_phy_device(struct phy_device *phydev)
 {
        return rtlgen_is_c45_match(phydev, RTL_8221B_VB_CG, false);
@@ -1118,9 +1142,21 @@ static int rtl8221b_vn_cg_c45_match_phy_device(struct phy_device *phydev)
        return rtlgen_is_c45_match(phydev, RTL_8221B_VN_CG, true);
 }
 
-static int rtl8251b_c22_match_phy_device(struct phy_device *phydev)
+static int rtl_internal_nbaset_match_phy_device(struct phy_device *phydev)
 {
-       return rtlgen_is_c45_match(phydev, RTL_8251B, false);
+       if (phydev->is_c45)
+               return false;
+
+       switch (phydev->phy_id) {
+       case RTL_GENERIC_PHYID:
+       case RTL_8221B:
+       case RTL_8251B:
+               break;
+       default:
+               return false;
+       }
+
+       return rtlgen_supports_2_5gbps(phydev) && !rtlgen_supports_mmd(phydev);
 }
 
 static int rtl8251b_c45_match_phy_device(struct phy_device *phydev)
@@ -1382,10 +1418,8 @@ static struct phy_driver realtek_drvs[] = {
                .resume         = rtlgen_resume,
                .read_page      = rtl821x_read_page,
                .write_page     = rtl821x_write_page,
-               .read_mmd       = rtl822x_read_mmd,
-               .write_mmd      = rtl822x_write_mmd,
        }, {
-               PHY_ID_MATCH_EXACT(0x001cc840),
+               .match_phy_device = rtl8221b_match_phy_device,
                .name           = "RTL8226B_RTL8221B 2.5Gbps PHY",
                .get_features   = rtl822x_get_features,
                .config_aneg    = rtl822x_config_aneg,
@@ -1396,8 +1430,6 @@ static struct phy_driver realtek_drvs[] = {
                .resume         = rtlgen_resume,
                .read_page      = rtl821x_read_page,
                .write_page     = rtl821x_write_page,
-               .read_mmd       = rtl822x_read_mmd,
-               .write_mmd      = rtl822x_write_mmd,
        }, {
                PHY_ID_MATCH_EXACT(0x001cc838),
                .name           = "RTL8226-CG 2.5Gbps PHY",
@@ -1475,8 +1507,9 @@ static struct phy_driver realtek_drvs[] = {
                .read_page      = rtl821x_read_page,
                .write_page     = rtl821x_write_page,
        }, {
-               .match_phy_device = rtl8251b_c22_match_phy_device,
-               .name           = "RTL8126A-internal 5Gbps PHY",
+               .match_phy_device = rtl_internal_nbaset_match_phy_device,
+               .name           = "Realtek Internal NBASE-T PHY",
+               .flags          = PHY_IS_INTERNAL,
                .get_features   = rtl822x_get_features,
                .config_aneg    = rtl822x_config_aneg,
                .read_status    = rtl822x_read_status,