]> www.infradead.org Git - users/hch/misc.git/commitdiff
net: stmmac: dwmac4: Fix high address display by updating reg_space[] from register...
authorLey Foon Tan <leyfoon.tan@starfivetech.com>
Mon, 21 Oct 2024 05:46:25 +0000 (13:46 +0800)
committerPaolo Abeni <pabeni@redhat.com>
Tue, 29 Oct 2024 10:29:40 +0000 (11:29 +0100)
The high address will display as 0 if the driver does not set the
reg_space[]. To fix this, read the high address registers and
update the reg_space[] accordingly.

Fixes: fbf68229ffe7 ("net: stmmac: unify registers dumps methods")
Signed-off-by: Ley Foon Tan <leyfoon.tan@starfivetech.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20241021054625.1791965-1-leyfoon.tan@starfivetech.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h

index e0165358c4ac88bb46adf17dcf449b08eafd5f6e..77b35abc6f6fa43a2cd88e020a3d6f6330bc22d8 100644 (file)
@@ -203,8 +203,12 @@ static void _dwmac4_dump_dma_regs(struct stmmac_priv *priv,
                readl(ioaddr + DMA_CHAN_TX_CONTROL(dwmac4_addrs, channel));
        reg_space[DMA_CHAN_RX_CONTROL(default_addrs, channel) / 4] =
                readl(ioaddr + DMA_CHAN_RX_CONTROL(dwmac4_addrs, channel));
+       reg_space[DMA_CHAN_TX_BASE_ADDR_HI(default_addrs, channel) / 4] =
+               readl(ioaddr + DMA_CHAN_TX_BASE_ADDR_HI(dwmac4_addrs, channel));
        reg_space[DMA_CHAN_TX_BASE_ADDR(default_addrs, channel) / 4] =
                readl(ioaddr + DMA_CHAN_TX_BASE_ADDR(dwmac4_addrs, channel));
+       reg_space[DMA_CHAN_RX_BASE_ADDR_HI(default_addrs, channel) / 4] =
+               readl(ioaddr + DMA_CHAN_RX_BASE_ADDR_HI(dwmac4_addrs, channel));
        reg_space[DMA_CHAN_RX_BASE_ADDR(default_addrs, channel) / 4] =
                readl(ioaddr + DMA_CHAN_RX_BASE_ADDR(dwmac4_addrs, channel));
        reg_space[DMA_CHAN_TX_END_ADDR(default_addrs, channel) / 4] =
@@ -225,8 +229,12 @@ static void _dwmac4_dump_dma_regs(struct stmmac_priv *priv,
                readl(ioaddr + DMA_CHAN_CUR_TX_DESC(dwmac4_addrs, channel));
        reg_space[DMA_CHAN_CUR_RX_DESC(default_addrs, channel) / 4] =
                readl(ioaddr + DMA_CHAN_CUR_RX_DESC(dwmac4_addrs, channel));
+       reg_space[DMA_CHAN_CUR_TX_BUF_ADDR_HI(default_addrs, channel) / 4] =
+               readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR_HI(dwmac4_addrs, channel));
        reg_space[DMA_CHAN_CUR_TX_BUF_ADDR(default_addrs, channel) / 4] =
                readl(ioaddr + DMA_CHAN_CUR_TX_BUF_ADDR(dwmac4_addrs, channel));
+       reg_space[DMA_CHAN_CUR_RX_BUF_ADDR_HI(default_addrs, channel) / 4] =
+               readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR_HI(dwmac4_addrs, channel));
        reg_space[DMA_CHAN_CUR_RX_BUF_ADDR(default_addrs, channel) / 4] =
                readl(ioaddr + DMA_CHAN_CUR_RX_BUF_ADDR(dwmac4_addrs, channel));
        reg_space[DMA_CHAN_STATUS(default_addrs, channel) / 4] =
index 17d9120db5fe90e5148026ae8447121420db2e4a..4f980dcd39582399616d49016b7548999b3f9cfd 100644 (file)
@@ -127,7 +127,9 @@ static inline u32 dma_chanx_base_addr(const struct dwmac4_addrs *addrs,
 #define DMA_CHAN_SLOT_CTRL_STATUS(addrs, x)    (dma_chanx_base_addr(addrs, x) + 0x3c)
 #define DMA_CHAN_CUR_TX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x44)
 #define DMA_CHAN_CUR_RX_DESC(addrs, x) (dma_chanx_base_addr(addrs, x) + 0x4c)
+#define DMA_CHAN_CUR_TX_BUF_ADDR_HI(addrs, x)  (dma_chanx_base_addr(addrs, x) + 0x50)
 #define DMA_CHAN_CUR_TX_BUF_ADDR(addrs, x)     (dma_chanx_base_addr(addrs, x) + 0x54)
+#define DMA_CHAN_CUR_RX_BUF_ADDR_HI(addrs, x)  (dma_chanx_base_addr(addrs, x) + 0x58)
 #define DMA_CHAN_CUR_RX_BUF_ADDR(addrs, x)     (dma_chanx_base_addr(addrs, x) + 0x5c)
 #define DMA_CHAN_STATUS(addrs, x)      (dma_chanx_base_addr(addrs, x) + 0x60)