#define AVIVO_D1CRTC_BLANK_CONTROL                              0x6084
 #define AVIVO_D1CRTC_INTERLACE_CONTROL                          0x6088
 #define AVIVO_D1CRTC_INTERLACE_STATUS                           0x608c
+#define AVIVO_D1CRTC_STATUS_POSITION                            0x60a0
 #define AVIVO_D1CRTC_FRAME_COUNT                                0x60a4
 #define AVIVO_D1CRTC_STEREO_CONTROL                             0x60c4
 
 #define AVIVO_D2CRTC_BLANK_CONTROL                              0x6884
 #define AVIVO_D2CRTC_INTERLACE_CONTROL                          0x6888
 #define AVIVO_D2CRTC_INTERLACE_STATUS                           0x688c
+#define AVIVO_D2CRTC_STATUS_POSITION                            0x68a0
 #define AVIVO_D2CRTC_FRAME_COUNT                                0x68a4
 #define AVIVO_D2CRTC_STEREO_CONTROL                             0x68c4
 
 
                        }
 
                } else {
+                       u32 position;
+                       u32 vbl;
+
                        radeon_sync_with_vblank(rdev);
 
+                       if (!radeon_pm_in_vbl(rdev))
+                               return;
+
+                       if (rdev->pm.active_crtcs & (1 << 0)) {
+                               vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
+                               position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
+                               position &= 0xfff;
+                               vbl &= 0xfff;
+
+                               if (position < vbl && position > 1)
+                                       return;
+                       }
+
+                       if (rdev->pm.active_crtcs & (1 << 1)) {
+                               vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
+                               position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
+                               position &= 0xfff;
+                               vbl &= 0xfff;
+
+                               if (position < vbl && position > 1)
+                                       return;
+                       }
+
                        if (sclk != rdev->pm.current_sclk) {
                                radeon_pm_debug_check_in_vbl(rdev, false);
                                radeon_set_engine_clock(rdev, sclk);
 
 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
+bool radeon_pm_in_vbl(struct radeon_device *rdev);
 bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
 void radeon_sync_with_vblank(struct radeon_device *rdev);
 
 
        mutex_unlock(&rdev->pm.mutex);
 }
 
-bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
+bool radeon_pm_in_vbl(struct radeon_device *rdev)
 {
        u32 stat_crtc = 0;
        bool in_vbl = true;
                                in_vbl = false;
                }
        }
+
+       return in_vbl;
+}
+
+bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
+{
+       u32 stat_crtc = 0;
+       bool in_vbl = radeon_pm_in_vbl(rdev);
+
        if (in_vbl == false)
                DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc,
                         finish ? "exit" : "entry");