sparc64: cache_line_size() returns larger value for cache line size.

SPARC currently returns L1 data cache line size (as low as 32 bytes on
some systems) though L2 and L3 cache line sizes may be higher.  As
cache_line_size() is used by code to align memory requests to prevent
unnecessary cache line sharing, this patch returns the max of L2 and L3
sizes, currently 64 bytes.

OraBug: 26045057

Signed-off-by: Chris Hyser <chris.hyser@oracle.com>
Reviewed-by: Rob Gardner <rob.gardner@oracle.com>
Signed-off-by: Shannon Nelson <shannon.nelson@oracle.com>

diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 3bbce983243cf472ef28f5455ed8f55c526e8f70..83820b13a8b613bd40cdaf3fce93d8b5821080cd 100644 (file)
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -135,6 +135,9 @@ config NEED_PER_CPU_EMBED_FIRST_CHUNK
 config NEED_PER_CPU_PAGE_FIRST_CHUNK
        def_bool y if SPARC64
 
+config ARCH_HAS_CACHE_LINE_SIZE
+       def_bool y if SPARC64
+
 config MMU
        bool
        default y

diff --git a/arch/sparc/include/asm/cache.h b/arch/sparc/include/asm/cache.h
index 5bb6991b48575026134498f743390ba598b20564..0bc9e0c42f1218587468a574b7ef46feb061ee75 100644 (file)
--- a/arch/sparc/include/asm/cache.h
+++ b/arch/sparc/include/asm/cache.h
@@ -12,6 +12,11 @@
 #define L1_CACHE_SHIFT 5
 #define L1_CACHE_BYTES 32
 
+#ifdef CONFIG_ARCH_HAS_CACHE_LINE_SIZE
+#define cache_line_size() max(local_cpu_data().l3_cache_line_size, \
+                             local_cpu_data().ecache_line_size)
+#endif
+
 #ifdef CONFIG_SPARC32
 #define SMP_CACHE_BYTES_SHIFT 5
 #else