drm/amd/display: OPP DPG test pattern

Create opp_set_test_pattern function with similar interface
and implementation as timing generator test pattern.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index ddc56700109b36e25280ab5cc90665a21cf03ad1..d7d027c7ae512680df4057007349faac636f98c8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -178,4 +178,41 @@ struct dc_bias_and_scale {
        uint16_t bias_blue;
 };
 
+enum test_pattern_dyn_range {
+       TEST_PATTERN_DYN_RANGE_VESA = 0,
+       TEST_PATTERN_DYN_RANGE_CEA
+};
+
+enum test_pattern_mode {
+       TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
+       TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
+       TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
+       TEST_PATTERN_MODE_VERTICALBARS,
+       TEST_PATTERN_MODE_HORIZONTALBARS,
+       TEST_PATTERN_MODE_SINGLERAMP_RGB,
+       TEST_PATTERN_MODE_DUALRAMP_RGB
+};
+
+enum test_pattern_color_format {
+       TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
+       TEST_PATTERN_COLOR_FORMAT_BPC_8,
+       TEST_PATTERN_COLOR_FORMAT_BPC_10,
+       TEST_PATTERN_COLOR_FORMAT_BPC_12
+};
+
+enum controller_dp_test_pattern {
+       CONTROLLER_DP_TEST_PATTERN_D102 = 0,
+       CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
+       CONTROLLER_DP_TEST_PATTERN_PRBS7,
+       CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
+       CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
+       CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
+       CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
+       CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
+       CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
+       CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
+       CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
+       CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
+};
+
 #endif /* __DAL_HW_SHARED_H__ */

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index 8c3a302fcd65b94efaa69d59cdffc586b833f313..42f2bb29a5fc8e14128ad2469af58491226ee670 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -284,7 +284,10 @@ struct opp_funcs {
 
        void (*opp_set_test_pattern)(
                        struct output_pixel_processor *opp,
-                       bool enable);
+                       enum controller_dp_test_pattern test_pattern,
+                       enum dc_color_depth color_depth,
+                       int width,
+                       int height);
 
        void (*opp_dpg_blank_enable)(
                        struct output_pixel_processor *opp,

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index e5c7e0e1db140c337ae70307530ad23a267b65ab..11a1d3672584ad2c72ff366fa55e7488c3c950bf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -26,6 +26,8 @@
 #ifndef __DAL_TIMING_GENERATOR_TYPES_H__
 #define __DAL_TIMING_GENERATOR_TYPES_H__
 
+#include "hw_shared.h"
+
 struct dc_bios;
 
 /* Contains CRTC vertical/horizontal pixel counters */
@@ -50,43 +52,6 @@ struct drr_params {
 #define LEFT_EYE_3D_PRIMARY_SURFACE 1
 #define RIGHT_EYE_3D_PRIMARY_SURFACE 0
 
-enum test_pattern_dyn_range {
-       TEST_PATTERN_DYN_RANGE_VESA = 0,
-       TEST_PATTERN_DYN_RANGE_CEA
-};
-
-enum test_pattern_mode {
-       TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,
-       TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,
-       TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,
-       TEST_PATTERN_MODE_VERTICALBARS,
-       TEST_PATTERN_MODE_HORIZONTALBARS,
-       TEST_PATTERN_MODE_SINGLERAMP_RGB,
-       TEST_PATTERN_MODE_DUALRAMP_RGB
-};
-
-enum test_pattern_color_format {
-       TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,
-       TEST_PATTERN_COLOR_FORMAT_BPC_8,
-       TEST_PATTERN_COLOR_FORMAT_BPC_10,
-       TEST_PATTERN_COLOR_FORMAT_BPC_12
-};
-
-enum controller_dp_test_pattern {
-       CONTROLLER_DP_TEST_PATTERN_D102 = 0,
-       CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,
-       CONTROLLER_DP_TEST_PATTERN_PRBS7,
-       CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,
-       CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,
-       CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,
-       CONTROLLER_DP_TEST_PATTERN_COLORRAMP,
-       CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
-       CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
-       CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
-       CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
-       CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
-};
-
 enum crtc_state {
        CRTC_STATE_VBLANK = 0,
        CRTC_STATE_VACTIVE