pata_efar: fix wrong PIO timings being programmed

* do not clear PIO timings for master when programming slave
* do not clear PIO timings for device on the other port when
  programming slave device

Both changes should be safe as this is how we have been doing
things in IDE slc90e66 host driver for years.

Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>

diff --git a/drivers/ata/pata_efar.c b/drivers/ata/pata_efar.c
index 2a6412f5d117b9c61e66c13380a4045d5877f599..540c36426303448e78a5df0fc30e5f0867a64312 100644 (file)
--- a/drivers/ata/pata_efar.c
+++ b/drivers/ata/pata_efar.c
@@ -2,6 +2,7 @@
  *    pata_efar.c - EFAR PIIX clone controller driver
  *
  *     (C) 2005 Red Hat
+ *     (C) 2009 Bartlomiej Zolnierkiewicz
  *
  *    Some parts based on ata_piix.c by Jeff Garzik and others.
  *
@@ -118,12 +119,12 @@ static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)
                int shift = 4 * ap->port_no;
                u8 slave_data;
 
-               idetm_data &= 0xCC0F;
+               idetm_data &= 0xFF0F;
                idetm_data |= (control << 4);
 
                /* Slave timing in separate register */
                pci_read_config_byte(dev, 0x44, &slave_data);
-               slave_data &= 0x0F << shift;
+               slave_data &= ap->port_no ? 0x0F : 0xF0;
                slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift;
                pci_write_config_byte(dev, 0x44, slave_data);
        }