#define ARM64_HAS_IRQ_PRIO_MASKING             42
 #define ARM64_HAS_DCPODP                       43
 #define ARM64_WORKAROUND_1463225               44
+#define ARM64_WORKAROUND_1319367               45
 
-#define ARM64_NCAPS                            45
+#define ARM64_NCAPS                            46
 
 #endif /* __ASM_CPUCAPS_H */
 
        return (need_wa > 0);
 }
 
-#ifdef CONFIG_HARDEN_EL2_VECTORS
+#if defined(CONFIG_HARDEN_EL2_VECTORS) || defined(CONFIG_ARM64_ERRATUM_1319367)
 
-static const struct midr_range arm64_harden_el2_vectors[] = {
+static const struct midr_range ca57_a72[] = {
        MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
        MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
        {},
        {
                .desc = "EL2 vector hardening",
                .capability = ARM64_HARDEN_EL2_VECTORS,
-               ERRATA_MIDR_RANGE_LIST(arm64_harden_el2_vectors),
+               ERRATA_MIDR_RANGE_LIST(ca57_a72),
        },
 #endif
        {
                .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
                .matches = has_cortex_a76_erratum_1463225,
        },
+#endif
+#ifdef CONFIG_ARM64_ERRATUM_1319367
+       {
+               .desc = "ARM erratum 1319367",
+               .capability = ARM64_WORKAROUND_1319367,
+               ERRATA_MIDR_RANGE_LIST(ca57_a72),
+       },
 #endif
        {
        }