drm/amdgpu/hdp5.2: do a posting read when flushing HDP

Need to read back to make sure the write goes through.

Cc: David Belanger <david.belanger@amd.com>
Reviewed-by: Frank Min <frank.min@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c b/drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c
index 29c3484ae1f1660a43c4e668f85ba23612db5039..f52552c5fa27b6df8295f31d191d4dbdbc3bea1a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v5_2.c
@@ -31,13 +31,15 @@
 static void hdp_v5_2_flush_hdp(struct amdgpu_device *adev,
                                struct amdgpu_ring *ring)
 {
-       if (!ring || !ring->funcs->emit_wreg)
+       if (!ring || !ring->funcs->emit_wreg) {
                WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2,
                        0);
-       else
+               RREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
+       } else {
                amdgpu_ring_emit_wreg(ring,
                        (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2,
                        0);
+       }
 }
 
 static void hdp_v5_2_update_mem_power_gating(struct amdgpu_device *adev,