return 0;
 }
 
+static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr)
+{
+       struct vega12_hwmgr *data =
+                       (struct vega12_hwmgr *)(hwmgr->backend);
+
+       data->uvd_power_gated = true;
+       data->vce_power_gated = true;
+
+       if (data->smu_features[GNLD_DPM_UVD].enabled)
+               data->uvd_power_gated = false;
+
+       if (data->smu_features[GNLD_DPM_VCE].enabled)
+               data->vce_power_gated = false;
+}
+
 static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)
 {
        struct vega12_hwmgr *data =
                }
        }
 
+       vega12_init_powergate_state(hwmgr);
+
        return 0;
 }
 
 {
        struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
 
+       if (data->vce_power_gated == bgate)
+               return;
+
        data->vce_power_gated = bgate;
        vega12_enable_disable_vce_dpm(hwmgr, !bgate);
 }
 {
        struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
 
+       if (data->uvd_power_gated == bgate)
+               return;
+
        data->uvd_power_gated = bgate;
        vega12_enable_disable_uvd_dpm(hwmgr, !bgate);
 }