GDMA_GENERATE_TEST_EQE          = 10,
        GDMA_CREATE_QUEUE               = 12,
        GDMA_DISABLE_QUEUE              = 13,
+       GDMA_ALLOCATE_RESOURCE_RANGE    = 22,
+       GDMA_DESTROY_RESOURCE_RANGE     = 24,
        GDMA_CREATE_DMA_REGION          = 25,
        GDMA_DMA_REGION_ADD_PAGES       = 26,
        GDMA_DESTROY_DMA_REGION         = 27,
 };
 
+#define GDMA_RESOURCE_DOORBELL_PAGE    27
+
 enum gdma_queue_type {
        GDMA_INVALID_QUEUE,
        GDMA_SQ,
        u32 db_id;
 }; /* HW DATA */
 
+struct gdma_allocate_resource_range_req {
+       struct gdma_req_hdr hdr;
+       u32 resource_type;
+       u32 num_resources;
+       u32 alignment;
+       u32 allocated_resources;
+};
+
+struct gdma_allocate_resource_range_resp {
+       struct gdma_resp_hdr hdr;
+       u32 allocated_resources;
+};
+
+struct gdma_destroy_resource_range_req {
+       struct gdma_req_hdr hdr;
+       u32 resource_type;
+       u32 num_resources;
+       u32 allocated_resources;
+};
+
 /* GDMA_CREATE_QUEUE */
 struct gdma_create_queue_req {
        struct gdma_req_hdr hdr;