clk: renesas: rcar-gen4: Use FIELD_GET()

Improve readability by using the FIELD_GET() helper instead of
open-coding the same operation, and by adding field definitions to get
rid of hardcoded values.

While at it, move register definitions that are only used inside the
rcar-gen4-cpg.c source file out of the rcar-gen4-cpg.h header file.
Add a "CPG_" prefix to SD0CKCR1.  Add comments where appropriate.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/fb19ad829738f02effa340fa04c178a162d41202.1721648548.git.geert+renesas@glider.be

diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c
index cd8799e04b37556eec58c0a26649775adcb6b31f..ae18470d9732ec3a943f1656e6e8319ec2df5dc4 100644 (file)
--- a/drivers/clk/renesas/rcar-gen4-cpg.c
+++ b/drivers/clk/renesas/rcar-gen4-cpg.c
@@ -55,6 +55,14 @@ static u32 cpg_mode __initdata;
 /* Fractional 8.25 PLL */
 #define CPG_PLLxCR0_NI8                GENMASK(27, 20) /* Integer mult. factor */
 
+#define CPG_PLLxCR_STC         GENMASK(30, 24) /* R_Car V3U PLLxCR */
+
+#define CPG_RPCCKCR            0x874   /* RPC Clock Freq. Control Register */
+
+#define CPG_SD0CKCR1           0x8a4   /* SD-IF0 Clock Freq. Control Reg. 1 */
+
+#define CPG_SD0CKCR1_SDSRC_SEL GENMASK(30, 29) /* SDSRC clock freq. select */
+
 /* PLL Clocks */
 struct cpg_pll_clk {
        struct clk_hw hw;
@@ -392,7 +400,7 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
 
        case CLK_TYPE_GEN4_PLL2X_3X:
                value = readl(base + core->offset);
-               mult = (((value >> 24) & 0x7f) + 1) * 2;
+               mult = (FIELD_GET(CPG_PLLxCR_STC, value) + 1) * 2;
                break;
 
        case CLK_TYPE_GEN4_Z:
@@ -400,7 +408,8 @@ struct clk * __init rcar_gen4_cpg_clk_register(struct device *dev,
                                          base, core->div, core->offset);
 
        case CLK_TYPE_GEN4_SDSRC:
-               div = ((readl(base + SD0CKCR1) >> 29) & 0x03) + 4;
+               value = readl(base + CPG_SD0CKCR1);
+               div = FIELD_GET(CPG_SD0CKCR1_SDSRC_SEL, value) + 4;
                break;
 
        case CLK_TYPE_GEN4_SDH:

diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h
index 006537e29e4eb10e214e52242965fc93fd456940..d0329ac84730d681d0b2741479acf8a27adbe076 100644 (file)
--- a/drivers/clk/renesas/rcar-gen4-cpg.h
+++ b/drivers/clk/renesas/rcar-gen4-cpg.h
@@ -67,9 +67,6 @@ struct rcar_gen4_cpg_pll_config {
        u8 osc_prediv;
 };
 
-#define CPG_RPCCKCR    0x874
-#define SD0CKCR1       0x8a4
-
 struct clk *rcar_gen4_cpg_clk_register(struct device *dev,
        const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
        struct clk **clks, void __iomem *base,